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Searched refs:RISCVSubtarget (Results 1 – 25 of 31) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSubtarget.cpp65 void RISCVSubtarget::anchor() {} in anchor()
67 RISCVSubtarget &
90 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, in RISCVSubtarget() function in RISCVSubtarget
106 const CallLowering *RISCVSubtarget::getCallLowering() const { in getCallLowering()
122 bool RISCVSubtarget::useConstantPoolForLargeInts() const { in useConstantPoolForLargeInts()
126 unsigned RISCVSubtarget::getMaxBuildIntsCost() const { in getMaxBuildIntsCost()
137 unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const { in getMaxRVVVectorSizeInBits()
162 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const { in getMinRVVVectorSizeInBits()
200 bool RISCVSubtarget::useRVVForFixedLengthVectors() const { in useRVVForFixedLengthVectors()
204 bool RISCVSubtarget::enableSubRegLiveness() const { in enableSubRegLiveness()
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H A DRISCVInstructionSelector.cpp35 const RISCVSubtarget &STI,
44 const RISCVSubtarget &STI;
52 const RISCVSubtarget *Subtarget = &STI;
70 const RISCVTargetMachine &TM, const RISCVSubtarget &STI, in RISCVInstructionSelector()
99 RISCVSubtarget &Subtarget, in createRISCVInstructionSelector()
H A DRISCVTargetMachine.cpp88 const RISCVSubtarget *
117 I = std::make_unique<RISCVSubtarget>(TargetTriple, CPU, TuneCPU, FS, ABIName, *this); in getSubtargetImpl()
148 const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>(); in createMachineScheduler()
159 const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>(); in createPostMachineScheduler()
H A DRISCVTargetMachine.h25 mutable StringMap<std::unique_ptr<RISCVSubtarget>> SubtargetMap;
33 const RISCVSubtarget *getSubtargetImpl(const Function &F) const override;
37 const RISCVSubtarget *getSubtargetImpl() const = delete;
H A DRISCVMakeCompressible.cpp147 const RISCVSubtarget &STI = MI.getMF()->getSubtarget<RISCVSubtarget>(); in isCompressibleLoad()
156 const RISCVSubtarget &STI = MI.getMF()->getSubtarget<RISCVSubtarget>(); in isCompressibleStore()
331 const RISCVSubtarget &STI = Fn.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
H A DRISCVLegalizerInfo.h20 class RISCVSubtarget; variable
25 RISCVLegalizerInfo(const RISCVSubtarget &ST);
H A DRISCVFrameLowering.h20 class RISCVSubtarget; variable
24 explicit RISCVFrameLowering(const RISCVSubtarget &STI) in RISCVFrameLowering()
76 const RISCVSubtarget &STI;
H A DRISCVMacroFusion.cpp57 const RISCVSubtarget &ST = static_cast<const RISCVSubtarget &>(TSI); in shouldScheduleAdjacent()
H A DRISCVRegisterInfo.cpp52 auto &Subtarget = MF->getSubtarget<RISCVSubtarget>(); in getCalleeSavedRegs()
84 if (MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(Reg)) in getReservedRegs()
117 return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg); in isAsmClobberable()
170 const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo(); in eliminateFrameIndex()
300 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in getCallPreservedMask()
356 return MF.getSubtarget<RISCVSubtarget>().hasStdExtC() ? 1 : 0; in getRegisterCostTableIndex()
H A DRISCV.h22 class RISCVSubtarget; variable
69 RISCVSubtarget &,
H A DRISCVSubtarget.h35 class RISCVSubtarget : public RISCVGenSubtargetInfo {
115 RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
123 RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
H A DRISCVInstrInfo.h26 class RISCVSubtarget; variable
47 explicit RISCVInstrInfo(RISCVSubtarget &STI);
186 const RISCVSubtarget &STI;
H A DRISCVCodeGenPrepare.cpp36 const RISCVSubtarget *ST;
159 ST = &TM.getSubtarget<RISCVSubtarget>(F); in runOnFunction()
H A DRISCVLegalizerInfo.cpp21 RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) { in RISCVLegalizerInfo()
H A DRISCVFrameLowering.cpp36 const auto &STI = MF.getSubtarget<RISCVSubtarget>(); in emitSCSPrologue()
87 const auto &STI = MF.getSubtarget<RISCVSubtarget>(); in emitSCSEpilogue()
348 static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; } in getFPReg()
351 static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; } in getSPReg()
887 if (MF.getSubtarget<RISCVSubtarget>().hasStdExtF()) { in determineCalleeSaves()
918 const auto &ST = MF.getSubtarget<RISCVSubtarget>(); in assignRVVStackObjectOffsets()
973 if (!MF.getSubtarget<RISCVSubtarget>().hasVInstructions()) in getScavSlotsNumForRVV()
1002 MF.getSubtarget<RISCVSubtarget>().getRegisterInfo(); in processFunctionBeforeFrameFinalized()
1070 return MF.getSubtarget<RISCVSubtarget>().hasVInstructions(); in hasRVVFrameObject()
H A DRISCVAsmPrinter.cpp42 const RISCVSubtarget *STI;
180 STI = &MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
H A DRISCVISelDAGToDAG.h24 const RISCVSubtarget *Subtarget = nullptr;
36 Subtarget = &MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
H A DRISCVTargetTransformInfo.h34 const RISCVSubtarget *ST;
37 const RISCVSubtarget *getST() const { return ST; } in getST()
H A DRISCVISelLowering.h23 class RISCVSubtarget; variable
348 const RISCVSubtarget &Subtarget;
352 const RISCVSubtarget &STI);
354 const RISCVSubtarget &getSubtarget() const { return Subtarget; } in getSubtarget()
H A DRISCVMachineFunctionInfo.h94 return MF.getSubtarget<RISCVSubtarget>().enableSaveRestore() &&
H A DCMakeLists.txt44 RISCVSubtarget.cpp
H A DRISCVMergeBaseOffset.cpp42 const RISCVSubtarget *ST = nullptr;
387 ST = &Fn.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
H A DRISCVSExtWRemoval.cpp432 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
H A DRISCVInsertVSETVLI.cpp1268 static bool hasFixedResult(const VSETVLIInfo &Info, const RISCVSubtarget &ST) { in hasFixedResult()
1295 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in doPRE()
1447 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
/llvm-project-15.0.7/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/
H A DBUILD.gn87 "RISCVSubtarget.cpp",

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