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/llvm-project-15.0.7/llvm/lib/Support/
H A DARMWinEH.cpp14 std::pair<uint16_t, uint32_t> SavedRegisterMask(const RuntimeFunction &RF, in SavedRegisterMask() argument
16 uint8_t NumRegisters = RF.Reg(); in SavedRegisterMask()
17 uint8_t RegistersVFP = RF.R(); in SavedRegisterMask()
18 uint8_t LinkRegister = RF.L(); in SavedRegisterMask()
19 uint8_t ChainedFrame = RF.C(); in SavedRegisterMask()
28 if (RF.Ret() != ReturnType::RT_POP) in SavedRegisterMask()
30 else if (!RF.H()) // If H == 0, we pop directly into Pc in SavedRegisterMask()
40 if ((PrologueFolding(RF) && Prologue) || (EpilogueFolding(RF) && !Prologue)) in SavedRegisterMask()
41 GPRMask |= (((1 << ((RF.StackAdjust() & 0x3) + 1)) - 1) in SavedRegisterMask()
42 << (~RF.StackAdjust() & 0x3)); in SavedRegisterMask()
/llvm-project-15.0.7/llvm/tools/llvm-readobj/
H A DARMWinEHPrinter.cpp1154 if (StackAdjustment(RF) && !PrologueFolding(RF)) in dumpPackedEntry()
1174 if (RF.H()) in dumpPackedEntry()
1184 if (StackAdjustment(RF) && !EpilogueFolding(RF)) in dumpPackedEntry()
1197 if (RF.L() == 0 || RF.Ret() != ReturnType::RT_POP) in dumpPackedEntry()
1254 if (RF.RegF()) in dumpPackedARM64Entry()
1273 if (RF.H()) { in dumpPackedARM64Entry()
1277 if (RF.RegI() > 0 || RF.RegF() > 0 || RF.CR() == 1) { in dumpPackedARM64Entry()
1286 int FloatRegs = RF.RegF() > 0 ? RF.RegF() + 1 : 0; in dumpPackedARM64Entry()
1292 } else if (I == 0 && RF.RegI() == 0 && RF.CR() != 1) { in dumpPackedARM64Entry()
1300 if (RF.CR() == 1 && (RF.RegI() % 2) == 0) { in dumpPackedARM64Entry()
[all …]
H A DWin64EHDumper.cpp244 const RuntimeFunction &RF) { in printRuntimeFunctionEntry() argument
246 formatSymbol(Ctx, Section, Offset + 0, RF.StartAddress)); in printRuntimeFunctionEntry()
248 formatSymbol(Ctx, Section, Offset + 4, RF.EndAddress, in printRuntimeFunctionEntry()
251 formatSymbol(Ctx, Section, Offset + 8, RF.UnwindInfoOffset)); in printRuntimeFunctionEntry()
361 const RuntimeFunction &RF) { in printRuntimeFunction() argument
363 printRuntimeFunctionEntry(Ctx, Section, SectionOffset, RF); in printRuntimeFunction()
368 Offset = Offset + RF.UnwindInfoOffset; in printRuntimeFunction()
371 uint64_t Address = Ctx.COFF.getImageBase() + RF.UnwindInfoOffset; in printRuntimeFunction()
375 Offset = RF.UnwindInfoOffset - XData->VirtualAddress; in printRuntimeFunction()
417 for (const auto &RF : RuntimeFunctions) { in printData() local
[all …]
H A DWin64EHDumper.h46 const RuntimeFunction &RF);
52 uint64_t SectionOffset, const RuntimeFunction &RF);
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86AsmBackend.cpp775 auto &Inst = RF.getInst(); in isFullyRelaxed()
784 if (!RF.getAllowAutoPadding()) in padInstructionViaPrefix()
790 if (!isFullyRelaxed(RF)) in padInstructionViaPrefix()
823 Code.append(RF.getContents().begin(), RF.getContents().end()); in padInstructionViaPrefix()
824 RF.getContents() = Code; in padInstructionViaPrefix()
838 if (isFullyRelaxed(RF)) in padInstructionViaRelaxation()
843 MCInst Relaxed = RF.getInst(); in padInstructionViaRelaxation()
856 RF.setInst(Relaxed); in padInstructionViaRelaxation()
857 RF.getContents() = Code; in padInstructionViaRelaxation()
858 RF.getFixups() = Fixups; in padInstructionViaRelaxation()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DARMWinEH.h188 inline bool PrologueFolding(const RuntimeFunction &RF) { in PrologueFolding() argument
189 return RF.StackAdjust() >= 0x3f4 && (RF.StackAdjust() & 0x4); in PrologueFolding()
193 inline bool EpilogueFolding(const RuntimeFunction &RF) { in EpilogueFolding() argument
194 return RF.StackAdjust() >= 0x3f4 && (RF.StackAdjust() & 0x8); in EpilogueFolding()
199 inline uint16_t StackAdjustment(const RuntimeFunction &RF) { in StackAdjustment() argument
200 uint16_t Adjustment = RF.StackAdjust(); in StackAdjustment()
208 std::pair<uint16_t, uint32_t> SavedRegisterMask(const RuntimeFunction &RF,
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonAsmBackend.cpp50 void ReplaceInstruction(MCCodeEmitter &E, MCRelaxableFragment &RF, in ReplaceInstruction() argument
55 E.encodeInstruction(HMB, VecOS, Fixups, *RF.getSubtargetInfo()); in ReplaceInstruction()
58 RF.setInst(HMB); in ReplaceInstruction()
59 RF.getContents() = Code; in ReplaceInstruction()
60 RF.getFixups() = Fixups; in ReplaceInstruction()
737 auto &RF = cast<MCRelaxableFragment>(*K); in finishLayout() local
738 auto &Inst = const_cast<MCInst &>(RF.getInst()); in finishLayout()
746 Context, *MCII, *RF.getSubtargetInfo(), Inst, in finishLayout()
754 *RF.getSubtargetInfo(), Inst); in finishLayout()
757 ReplaceInstruction(Asm.getEmitter(), RF, Inst); in finishLayout()
[all …]
/llvm-project-15.0.7/llvm/tools/llvm-objdump/
H A DCOFFDump.cpp664 if (!RF.StartAddress) in printRuntimeFunction()
668 static_cast<uint32_t>(RF.StartAddress)) in printRuntimeFunction()
670 static_cast<uint32_t>(RF.EndAddress)) in printRuntimeFunction()
674 if (Obj->getRvaPtr(RF.UnwindInfoOffset, addr)) in printRuntimeFunction()
694 RF.StartAddress); in printRuntimeFunctionRels()
701 RF.EndAddress); in printRuntimeFunctionRels()
708 RF.UnwindInfoOffset); in printRuntimeFunctionRels()
722 UnwindInfoOffset += RF.UnwindInfoOffset; in printRuntimeFunctionRels()
748 for (const RuntimeFunction &RF : RFs) in printCOFFUnwindInfo() local
749 printRuntimeFunction(Obj, RF); in printCOFFUnwindInfo()
[all …]
/llvm-project-15.0.7/llvm/unittests/ExecutionEngine/Orc/
H A DWrapperFunctionUtilsTest.cpp113 auto RF = RP.get_future(); in voidNoopAsyncWrapper() local
119 return RF.get(); in voidNoopAsyncWrapper()
125 auto RF = RP.get_future(); in addAsyncWrapper() local
133 return RF.get(); in addAsyncWrapper()
H A DExecutionSessionWrapperFunctionCallsTest.cpp99 auto RF = RP.get_future(); in TEST() local
116 EXPECT_EQ(RF.get(), (int32_t)3); in TEST()
/llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp88 const MCRegisterFileDesc &RF = Info.RegisterFiles[I]; in initialize() local
89 assert(RF.NumPhysRegs && "Invalid PRF with zero physical registers!"); in initialize()
93 unsigned Length = RF.NumRegisterCostEntries; in initialize()
95 &Info.RegisterCostTable[RF.RegisterCostEntryIdx]; in initialize()
96 addRegisterFile(RF, ArrayRef<MCRegisterCostEntry>(FirstElt, Length)); in initialize()
147 void RegisterFile::addRegisterFile(const MCRegisterFileDesc &RF, in addRegisterFile() argument
155 RegisterFiles.emplace_back(RF.NumPhysRegs, RF.MaxMovesEliminatedPerCycle, in addRegisterFile()
156 RF.AllowZeroMoveEliminationOnly); in addRegisterFile()
H A DResourceManager.cpp348 for (const ResourceRef &RF : ResourcesFreed) in cycleEvent() local
349 BusyResources.erase(RF); in cycleEvent()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dmisched-fusion-addr.ll86 ; CHECK: adrp [[RF:x[0-9]+]], var_float
87 ; CHECK-NEXT: str {{s[0-9]+}}, [[[RF]], {{#?}}:lo12:var_float]
97 ; CHECK: adrp [[RF:x[0-9]+]], var_float
98 ; CHECK-NEXT: ldr {{s[0-9]+}}, [[[RF]], {{#?}}:lo12:var_float]
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DTFUtils.cpp246 auto *RF = FeatureLists[FeatureID] in addNewTensor() local
250 RF->Resize(Spec.getElementCount(), 0.0); in addNewTensor()
251 return reinterpret_cast<char *>(RF->mutable_data()); in addNewTensor()
253 auto *RF = FeatureLists[FeatureID] in addNewTensor() local
257 RF->Resize(Spec.getElementCount(), 0); in addNewTensor()
258 return reinterpret_cast<char *>(RF->mutable_data()); in addNewTensor()
H A DCallGraph.cpp130 if (Function *RF = RHS->getFunction()) in print() local
131 return LF->getName() < RF->getName(); in print()
/llvm-project-15.0.7/llvm/tools/llvm-cvtres/
H A Dllvm-cvtres.cpp186 WindowsResource *RF = Binary.get(); in main() local
190 ResourceEntryRef Entry = error(RF->getHeadEntry()); in main()
200 error(Parser.parse(RF, Duplicates)); in main()
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCompressInstEmitter.cpp119 std::vector<Record *> RF, IndexedMap<OpData> &SourceMap, in CompressPat()
121 : Source(S), Dest(D), PatReqFeatures(RF), SourceOperandMap(SourceMap), in CompressPat()
477 std::vector<Record *> RF = Rec->getValueAsListOfDefs("Predicates"); in evaluateCompressPat() local
478 copy_if(RF, std::back_inserter(PatReqFeatures), [](Record *R) { in evaluateCompressPat()
685 std::vector<Record *> RF = Dest.TheDef->getValueAsListOfDefs("Predicates"); in emitCompressInstEmitter() local
686 copy_if(RF, std::back_inserter(ReqFeatures), [](Record *R) { in emitCompressInstEmitter()
H A DCodeGenSchedule.cpp1844 for (Record *RF : RegisterFileDefs) { in collectRegisterFiles()
1847 CodeGenProcModel &PM = getProcModel(RF->getValueAsDef("SchedModel")); in collectRegisterFiles()
1848 PM.RegisterFiles.emplace_back(CodeGenRegisterFile(RF->getName(),RF)); in collectRegisterFiles()
1851 RF->getValueAsInt("MaxMovesEliminatedPerCycle"); in collectRegisterFiles()
1853 RF->getValueAsBit("AllowZeroMoveEliminationOnly"); in collectRegisterFiles()
1857 CGRF.NumPhysRegs = RF->getValueAsInt("NumPhysRegs"); in collectRegisterFiles()
1859 PrintFatalError(RF->getLoc(), in collectRegisterFiles()
1863 RecVec RegisterClasses = RF->getValueAsListOfDefs("RegClasses"); in collectRegisterFiles()
1864 std::vector<int64_t> RegisterCosts = RF->getValueAsListOfInts("RegCosts"); in collectRegisterFiles()
1865 ListInit *MoveElimInfo = RF->getValueAsListInit("AllowMoveElimination"); in collectRegisterFiles()
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Df16-instructions.ll197 ; CHECK-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]];
855 ; CHECK-NOFTZ: sqrt.rn.f32 [[RF:%f[0-9]+]], [[AF]];
858 ; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]];
877 ; CHECK: sin.approx.f32 [[RF:%f[0-9]+]], [[AF]];
878 ; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]];
890 ; CHECK: cos.approx.f32 [[RF:%f[0-9]+]], [[AF]];
891 ; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]];
962 ; CHECK-NOFTZ: abs.f32 [[RF:%f[0-9]+]], [[AF]];
965 ; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]];
982 ; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]];
[all …]
/llvm-project-15.0.7/clang/lib/Interpreter/
H A DInterpreter.cpp164 llvm::ArrayRef<const char *> RF = llvm::makeArrayRef(ClangArgv); in create() local
165 std::unique_ptr<driver::Compilation> Compilation(Driver.BuildCompilation(RF)); in create()
/llvm-project-15.0.7/llvm/lib/ExecutionEngine/Interpreter/
H A DExternalFunctions.cpp275 std::map<const Function *, RawFunc>::iterator RF = RawFunctions->find(F); in callExternalFunction() local
277 if (RF == RawFunctions->end()) { in callExternalFunction()
285 RawFn = RF->second; in callExternalFunction()
/llvm-project-15.0.7/clang/lib/ASTMatchers/
H A DASTMatchFinder.cpp510 if (auto *RF = dyn_cast<CXXForRangeStmt>(S)) { in dataTraverseNode() local
513 TraverseStmt(RF->getInit()); in dataTraverseNode()
515 match(*RF->getLoopVariable()); in dataTraverseNode()
516 TraverseStmt(RF->getRangeInit()); in dataTraverseNode()
520 for (auto *SubStmt : RF->children()) { in dataTraverseNode()
521 if (SubStmt != RF->getBody()) in dataTraverseNode()
525 TraverseStmt(RF->getBody()); in dataTraverseNode()
/llvm-project-15.0.7/llvm/test/Transforms/AlignmentFromAssumptions/
H A Damdgpu-crash.ll10 define void @"_ZN44_$LT$$RF$T$u20$as$u20$core..fmt..Display$GT$3fmt17h7b1d039c7ff5e1feE"() {
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCAssembler.cpp890 MCRelaxableFragment &RF = cast<MCRelaxableFragment>(Frag); in layout() local
891 Fixups = RF.getFixups(); in layout()
892 Contents = RF.getContents(); in layout()
893 STI = RF.getSubtargetInfo(); in layout()
894 assert(!RF.hasInstructions() || STI != nullptr); in layout()
/llvm-project-15.0.7/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h212 void addRegisterFile(const MCRegisterFileDesc &RF,

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