Home
last modified time | relevance | path

Searched refs:RES (Results 1 – 25 of 331) sorted by relevance

12345678910>>...14

/llvm-project-15.0.7/llvm/test/tools/gold/X86/
H A Dcomdat.ll35 ; RES: 1.o,f1,plx{{$}}
36 ; RES: 1.o,v1,px{{$}}
37 ; RES: 1.o,r11,px{{$}}
38 ; RES: 1.o,r12,px{{$}}
39 ; RES: 1.o,a11,px{{$}}
40 ; RES: 1.o,a12,px{{$}}
41 ; RES: 1.o,a13,px{{$}}
42 ; RES: 1.o,a14,px{{$}}
43 ; RES: 1.o,a15,px{{$}}
45 ; RES: 2.o,f1,l{{$}}
[all …]
H A Demit-llvm.ll110 ; RES: .o,f1,pl{{$}}
111 ; RES: .o,f2,pl{{$}}
112 ; RES: .o,f3,px{{$}}
113 ; RES: .o,f4,p{{$}}
114 ; RES: .o,f5,px{{$}}
115 ; RES: .o,f6,p{{$}}
120 ; RES: .o,g2,p{{$}}
121 ; RES: .o,g3,p{{$}}
124 ; RES: .o,g6,p{{$}}
125 ; RES: .o,g7,{{$}}
[all …]
/llvm-project-15.0.7/llvm/test/Instrumentation/PoisonChecking/
H A Dbasic-flag-validation.ll9 ; CHECK-NEXT: ret i32 [[RES]]
22 ; CHECK-NEXT: ret i32 [[RES]]
35 ; CHECK-NEXT: ret i32 [[RES]]
51 ; CHECK-NEXT: ret i32 [[RES]]
60 ; CHECK-NEXT: ret i32 [[RES]]
73 ; CHECK-NEXT: ret i32 [[RES]]
86 ; CHECK-NEXT: ret i32 [[RES]]
102 ; CHECK-NEXT: ret i32 [[RES]]
111 ; CHECK-NEXT: ret i32 [[RES]]
124 ; CHECK-NEXT: ret i32 [[RES]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dreduction-shufflevector.ll7 ; CHECK-NEXT: ret i32 [[RES]]
17 ; CHECK-NEXT: ret i32 [[RES]]
27 ; CHECK-NEXT: ret i32 [[RES]]
37 ; CHECK-NEXT: ret i32 [[RES]]
47 ; CHECK-NEXT: ret i32 [[RES]]
57 ; CHECK-NEXT: ret i32 [[RES]]
67 ; CHECK-NEXT: ret i32 [[RES]]
77 ; CHECK-NEXT: ret i32 [[RES]]
131 ; CHECK-NEXT: ret i32 [[RES]]
142 ; CHECK-NEXT: ret i32 [[RES]]
[all …]
H A Dpow_fp_int.ll10 ; CHECK-NEXT: ret double [[RES]]
23 ; CHECK-NEXT: ret double [[RES]]
56 ; CHECK-NEXT: ret double [[RES]]
70 ; CHECK-NEXT: ret double [[RES]]
83 ; CHECK-NEXT: ret double [[RES]]
97 ; CHECK-NEXT: ret double [[RES]]
109 ; CHECK-NEXT: ret double [[RES]]
122 ; CHECK-NEXT: ret double [[RES]]
156 ; CHECK-NEXT: ret double [[RES]]
169 ; CHECK-NEXT: ret double [[RES]]
[all …]
H A Dselect-safe-impliedcond-transforms.ll8 ; CHECK-NEXT: ret i1 [[RES]]
41 ; CHECK-NEXT: ret i1 [[RES]]
54 ; CHECK-NEXT: ret i1 [[RES]]
67 ; CHECK-NEXT: ret i1 [[RES]]
80 ; CHECK-NEXT: ret i1 [[RES]]
93 ; CHECK-NEXT: ret i1 [[RES]]
106 ; CHECK-NEXT: ret i1 [[RES]]
119 ; CHECK-NEXT: ret i1 [[RES]]
132 ; CHECK-NEXT: ret i1 [[RES]]
145 ; CHECK-NEXT: ret i1 [[RES]]
[all …]
H A Dnonnull-select.ll23 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND:%.*]], i32* [[P:%.*]], i32* null
24 ; CHECK-NEXT: ret i32* [[RES]]
32 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND:%.*]], i32* null, i32* [[P:%.*]]
33 ; CHECK-NEXT: ret i32* [[RES]]
41 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[COND:%.*]], i32* [[P:%.*]], i32* null
42 ; CHECK-NEXT: ret i32* [[RES]]
51 ; CHECK-NEXT: ret i32* [[RES]]
61 ; CHECK-NEXT: call void @f(i32* nonnull [[RES]])
72 ; CHECK-NEXT: call void @f(i32* nonnull [[RES]])
83 ; CHECK-NEXT: call void @f(i32* noundef nonnull [[RES]])
[all …]
H A Dsincospi.ll30 ; CHECK-FLOAT-IN-VEC-NEXT: ret float [[RES]]
40 ; CHECK-NEXT: ret float [[RES]]
47 ; CHECK-NO-SINCOS-NEXT: ret float [[RES]]
75 ; CHECK-NEXT: ret float [[RES]]
81 ; CHECK-NO-SINCOS-NEXT: ret float [[RES]]
110 ; CHECK-NEXT: ret double [[RES]]
117 ; CHECK-NO-SINCOS-NEXT: ret double [[RES]]
145 ; CHECK-NEXT: ret double [[RES]]
151 ; CHECK-NO-SINCOS-NEXT: ret double [[RES]]
172 ; CHECK-NEXT: ret double [[RES]]
[all …]
H A Dgep-vector-indices.ll7 ; CHECK-NEXT: ret i32* [[RES]]
17 ; CHECK-NEXT: ret i32* [[RES]]
30 ; CHECK-NEXT: ret i32* [[RES]]
41 ; CHECK-NEXT: ret i32* [[RES]]
52 ; CHECK-NEXT: ret i32* [[RES]]
65 ; CHECK-NEXT: ret i32* [[RES]]
78 ; CHECK-NEXT: ret float* [[RES]]
89 ; CHECK-NEXT: ret float* [[RES]]
103 ; CHECK-NEXT: ret i32* [[RES]]
114 ; CHECK-NEXT: ret i32* [[RES]]
[all …]
H A Dpow_fp_int16.ll10 ; CHECK-NEXT: ret double [[RES]]
23 ; CHECK-NEXT: ret double [[RES]]
56 ; CHECK-NEXT: ret double [[RES]]
70 ; CHECK-NEXT: ret double [[RES]]
83 ; CHECK-NEXT: ret double [[RES]]
97 ; CHECK-NEXT: ret double [[RES]]
109 ; CHECK-NEXT: ret double [[RES]]
122 ; CHECK-NEXT: ret double [[RES]]
156 ; CHECK-NEXT: ret double [[RES]]
168 ; CHECK-NEXT: ret double [[RES]]
[all …]
H A Dstrict-sub-underflow-check-to-comparison-of-sub-operands.ll14 ; CHECK-NEXT: [[RES:%.*]] = icmp uge i8 [[BASE]], [[OFFSET]]
15 ; CHECK-NEXT: ret i1 [[RES]]
31 ; CHECK-NEXT: [[RES:%.*]] = icmp ult i8 [[BASE]], [[OFFSET]]
32 ; CHECK-NEXT: ret i1 [[RES]]
49 ; CHECK-NEXT: [[RES:%.*]] = icmp uge i8 [[BASE]], [[OFFSET]]
50 ; CHECK-NEXT: ret i1 [[RES]]
68 ; CHECK-NEXT: [[RES:%.*]] = icmp ult i8 [[BASE]], [[OFFSET]]
69 ; CHECK-NEXT: ret i1 [[RES]]
86 ; CHECK-NEXT: [[RES:%.*]] = icmp ult i8 [[ADJUSTED]], [[BASE]]
87 ; CHECK-NEXT: ret i1 [[RES]]
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/SPIRV/Transforms/
H A Dgl-canonicalize.mlir12 // CHECK-NEXT: spv.ReturnValue [[RES]]
27 // CHECK-NEXT: spv.ReturnValue [[RES]]
42 // CHECK-NEXT: spv.ReturnValue [[RES]]
57 // CHECK-NEXT: spv.ReturnValue [[RES]]
72 // CHECK-NEXT: spv.ReturnValue [[RES]]
87 // CHECK-NEXT: spv.ReturnValue [[RES]]
102 // CHECK-NEXT: spv.ReturnValue [[RES]]
117 // CHECK-NEXT: spv.ReturnValue [[RES]]
132 // CHECK-NEXT: spv.ReturnValue [[RES]]
147 // CHECK-NEXT: spv.ReturnValue [[RES]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A Delm_copy.ll33 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
56 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
79 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
105 ; MIPS32-DAG: sw [[RD1]], 0([[RES]])
106 ; MIPS32-DAG: sw [[RD2]], 4([[RES]])
107 ; MIPS64-DAG: sd [[RD]], 0([[RES]])
130 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
153 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
203 ; MIPS32-DAG: sw [[RD1]], 0([[RES]])
204 ; MIPS32-DAG: sw [[RD2]], 4([[RES]])
[all …]
/llvm-project-15.0.7/llvm/test/LTO/Resolution/X86/
H A Dalias-alias.ll5 ; RUN: FileCheck --check-prefix=RES %s < %t3.o.resolution.txt
14 ; RES: 1.o{{$}}
15 ; RES-NEXT: {{^}}-r={{.*}}1.o,c,p{{$}}
16 ; RES-NEXT: {{^}}-r={{.*}}1.o,a,p{{$}}
17 ; RES-NEXT: {{^}}-r={{.*}}1.o,b,{{$}}
18 ; RES-NEXT: 2.o{{$}}
19 ; RES-NEXT: {{^}}-r={{.*}}2.o,a,{{$}}
20 ; RES-NEXT: {{^}}-r={{.*}}2.o,d,px{{$}}
H A Dalias.ll5 ; RUN: FileCheck --check-prefix=RES %s < %t3.o.resolution.txt
12 ; RES: 2.o{{$}}
13 ; RES: {{^}}-r={{.*}}2.o,a,px{{$}}
14 ; RES: 1.o{{$}}
15 ; RES: {{^}}-r={{.*}}1.o,b,px{{$}}
16 ; RES: {{^}}-r={{.*}}1.o,a,{{$}}
/llvm-project-15.0.7/llvm/test/Transforms/TypePromotion/ARM/
H A Dwrapping.ll10 ; CHECK-NEXT: ret i16 [[RES]]
25 ; CHECK-NEXT: ret i16 [[RES]]
40 ; CHECK-NEXT: ret i16 [[RES]]
55 ; CHECK-NEXT: ret i16 [[RES]]
69 ; CHECK-NEXT: ret i32 [[RES]]
82 ; CHECK-NEXT: ret i32 [[RES]]
95 ; CHECK-NEXT: ret i32 [[RES]]
109 ; CHECK-NEXT: ret i32 [[RES]]
123 ; CHECK-NEXT: ret i32 [[RES]]
137 ; CHECK-NEXT: ret i32 [[RES]]
[all …]
H A Dicmps.ll10 ; CHECK-NEXT: ret i32 [[RES]]
25 ; CHECK-NEXT: ret i32 [[RES]]
40 ; CHECK-NEXT: ret i32 [[RES]]
55 ; CHECK-NEXT: ret i32 [[RES]]
71 ; CHECK-NEXT: ret i32 [[RES]]
86 ; CHECK-NEXT: ret i32 [[RES]]
101 ; CHECK-NEXT: ret i32 [[RES]]
116 ; CHECK-NEXT: ret i32 [[RES]]
134 ; CHECK-NEXT: ret i32 [[RES]]
155 ; CHECK-NEXT: ret i32 [[RES]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/Fast-ISel/
H A Dlogopm.ll41 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
43 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
64 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
88 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
114 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
134 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
157 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
183 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
204 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
227 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
[all …]
H A Dshftopm.ll28 ; CHECK-DAG: sllv $[[RES:[0-9]+]], $[[S1]], $[[S2]]
29 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]])
44 ; CHECK: sll $[[RES:[0-9]+]], $[[S1]], 5
46 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]])
67 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]])
81 ; CHECK: srl $[[RES:[0-9]+]], $[[US1]], 4
83 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]])
101 ; CHECK: srav $[[RES:[0-9]+]], $[[S1]], $[[S2]]
103 ; CHECK: sh $[[RES]], 0($[[S3_ADDR]])
118 ; CHECK: sra $[[RES:[0-9]+]], $[[S1]], 2
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dcmp-alloca-offsets.ll17 ; CHECK-NEXT: [[RES:%.*]] = icmp ne ptr [[A]], [[B_OFF]]
18 ; CHECK-NEXT: ret i1 [[RES]]
34 ; CHECK-NEXT: ret i1 [[RES]]
51 ; CHECK-NEXT: ret i1 [[RES]]
69 ; CHECK-NEXT: ret i1 [[RES]]
99 ; CHECK-NEXT: ret i1 [[RES]]
117 ; CHECK-NEXT: ret i1 [[RES]]
135 ; CHECK-NEXT: ret i1 [[RES]]
153 ; CHECK-NEXT: ret i1 [[RES]]
171 ; CHECK-NEXT: ret i1 [[RES]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/X86/
H A Dx86-shuffle-sink-inseltpoison.ll19 ; CHECK-SSE2-NEXT: ret <16 x i8> [[RES]]
28 ; CHECK-XOP-NEXT: ret <16 x i8> [[RES]]
38 ; CHECK-AVX-NEXT: ret <16 x i8> [[RES]]
60 ; CHECK-SSE2-NEXT: ret <8 x i16> [[RES]]
69 ; CHECK-XOP-NEXT: ret <8 x i16> [[RES]]
79 ; CHECK-AVX2-NEXT: ret <8 x i16> [[RES]]
109 ; CHECK-NEXT: ret <4 x i32> [[RES]]
140 ; CHECK-XOP-NEXT: ret <4 x i32> [[RES]]
149 ; CHECK-AVX-NEXT: ret <4 x i32> [[RES]]
180 ; CHECK-XOP-NEXT: ret <2 x i64> [[RES]]
[all …]
H A Dx86-shuffle-sink.ll19 ; CHECK-SSE2-NEXT: ret <16 x i8> [[RES]]
28 ; CHECK-XOP-NEXT: ret <16 x i8> [[RES]]
38 ; CHECK-AVX-NEXT: ret <16 x i8> [[RES]]
60 ; CHECK-SSE2-NEXT: ret <8 x i16> [[RES]]
69 ; CHECK-XOP-NEXT: ret <8 x i16> [[RES]]
79 ; CHECK-AVX2-NEXT: ret <8 x i16> [[RES]]
109 ; CHECK-NEXT: ret <4 x i32> [[RES]]
140 ; CHECK-XOP-NEXT: ret <4 x i32> [[RES]]
149 ; CHECK-AVX-NEXT: ret <4 x i32> [[RES]]
180 ; CHECK-XOP-NEXT: ret <2 x i64> [[RES]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dextract_vector_elt-i16.ll171 ; SI: buffer_store_short [[RES]]
172 ; VI: flat_load_dword [[RES:v[0-9]+]]
173 ; VI: flat_store_short v[{{[0-9:]+}}], [[RES]]
189 ; SI: buffer_store_short [[RES]]
190 ; VI: flat_load_dword [[RES:v[0-9]+]]
191 ; VI: flat_store_short v[{{[0-9:]+}}], [[RES]]
220 ; SI: buffer_store_short [[RES]]
221 ; VI: flat_load_dword [[RES:v[0-9]+]]
222 ; VI: flat_store_short v[{{[0-9:]+}}], [[RES]]
238 ; SI: buffer_store_short [[RES]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dvector-promotion.ll133 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
152 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
171 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
190 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
209 ; IR-BOTH-NEXT: store float [[RES]], float* %dest
228 ; IR-BOTH-NEXT: store float [[RES]], float* %dest
244 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
261 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
282 ; IR-BOTH-NEXT: store float [[RES]], float* %dest
348 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-transfer-to-vector-load-store.mlir48 // CHECK-NEXT: return %[[RES]] : vector<4xf32>
66 // CHECK-NEXT: return %[[RES]] : vector<2x4xf32>
84 // CHECK-NEXT: return %[[RES]] : vector<2x4xf32>
104 // CHECK-NEXT: return %[[RES]] : vector<1x2x4xf32>
124 // CHECK-NEXT: return %[[RES]] : vector<2x4xf32>
144 // CHECK-NEXT: return %[[RES]] : vector<4xf32>
161 // CHECK-NEXT: return %[[RES]] : vector<4xf32>
182 // CHECK-NEXT: return %[[RES]] : vector<4xf32>
201 // CHECK-NEXT: return %[[RES]] : vector<4xf32>
218 // CHECK-NEXT: return %[[RES]] : vector<1xf32>
[all …]

12345678910>>...14