Lines Matching refs:RES

6 ; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[X:%.*]])
7 ; CHECK-NEXT:    ret i32 [[RES]]
16 ; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[X:%.*]])
17 ; CHECK-NEXT:    ret i32 [[RES]]
26 ; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[X:%.*]])
27 ; CHECK-NEXT:    ret i32 [[RES]]
36 ; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> [[X:%.*]])
37 ; CHECK-NEXT:    ret i32 [[RES]]
46 ; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[X:%.*]])
47 ; CHECK-NEXT:    ret i32 [[RES]]
56 ; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[X:%.*]])
57 ; CHECK-NEXT:    ret i32 [[RES]]
66 ; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[X:%.*]])
67 ; CHECK-NEXT:    ret i32 [[RES]]
76 ; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[X:%.*]])
77 ; CHECK-NEXT:    ret i32 [[RES]]
86 ; CHECK-NEXT:    [[RES:%.*]] = call nnan nsz float @llvm.vector.reduce.fmax.v4f32(<4 x float> [[X:%…
87 ; CHECK-NEXT:    ret float [[RES]]
96 ; CHECK-NEXT:    [[RES:%.*]] = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> [[X:%.*]])
97 ; CHECK-NEXT:    ret float [[RES]]
106 ; CHECK-NEXT:    [[RES:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v4f32(float [[A:%.*]], <…
107 ; CHECK-NEXT:    ret float [[RES]]
116 ; CHECK-NEXT:    [[RES:%.*]] = call reassoc float @llvm.vector.reduce.fmul.v4f32(float [[A:%.*]], <…
117 ; CHECK-NEXT:    ret float [[RES]]
130 ; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[SHUF]])
131 ; CHECK-NEXT:    ret i32 [[RES]]
141 ; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[SHUF]])
142 ; CHECK-NEXT:    ret i32 [[RES]]
152 ; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[SHUF]])
153 ; CHECK-NEXT:    ret i32 [[RES]]
163 ; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> [[SHUF]])
164 ; CHECK-NEXT:    ret i32 [[RES]]
174 ; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[SHUF]])
175 ; CHECK-NEXT:    ret i32 [[RES]]
185 ; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[SHUF]])
186 ; CHECK-NEXT:    ret i32 [[RES]]
196 ; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[SHUF]])
197 ; CHECK-NEXT:    ret i32 [[RES]]
207 ; CHECK-NEXT:    [[RES:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[SHUF]])
208 ; CHECK-NEXT:    ret i32 [[RES]]
218 ; CHECK-NEXT:    [[RES:%.*]] = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> [[SHUF]])
219 ; CHECK-NEXT:    ret float [[RES]]
229 ; CHECK-NEXT:    [[RES:%.*]] = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> [[SHUF]])
230 ; CHECK-NEXT:    ret float [[RES]]
240 ; CHECK-NEXT:    [[RES:%.*]] = call float @llvm.vector.reduce.fadd.v4f32(float [[A:%.*]], <4 x floa…
241 ; CHECK-NEXT:    ret float [[RES]]
251 ; CHECK-NEXT:    [[RES:%.*]] = call float @llvm.vector.reduce.fmul.v4f32(float [[A:%.*]], <4 x floa…
252 ; CHECK-NEXT:    ret float [[RES]]