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Searched refs:RCP (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Drcp-pattern.ll8 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
9 ; GCN: buffer_store_dword [[RCP]]
20 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[SRC]]
21 ; GCN: buffer_store_dword [[RCP]]
33 ; GCN: buffer_store_dword [[RCP]]
45 ; GCN: buffer_store_dword [[RCP]]
57 ; GCN: buffer_store_dword [[RCP]]
69 ; GCN: buffer_store_dword [[RCP]]
82 ; GCN: buffer_store_dword [[RCP]]
94 ; GCN: buffer_store_dword [[RCP]]
[all …]
H A Dfdiv32-to-rcp-folding.ll11 ; GCN-DENORM: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[PRESCALED]]
12 ; GCN-DENORM: v_mul_f32_e32 [[OUT:v[0-9]+]], [[SCALE]], [[RCP]]
31 ; GCN-DENORM: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[PRESCALED]]
32 ; GCN-DENORM: v_mul_f32_e32 [[OUT:v[0-9]+]], [[SCALE]], [[RCP]]
51 ; GCN-DENORM: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[PRESCALED]]
72 ; GCN-DENORM: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[PRESCALED]]
336 ; GCN-FLUSH: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[PRESCALED]]
349 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[VAL]]
360 ; GCN: v_rcp_f32_e64 [[RCP:v[0-9]+]], -[[VAL]]
371 ; GCN: v_rcp_f32_e64 [[RCP:v[0-9]+]], -[[VAL]]
[all …]
H A Dselect-fabs-fneg-extract-legacy.ll10 ; GCN: v_rcp_legacy_f32_e32 [[RCP:v[0-9]+]], [[X]]
11 ; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], -2.0, [[RCP]], vcc
H A Dfdiv.ll105 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
106 ; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
122 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
123 ; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
137 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
138 ; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
152 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
153 ; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
H A Drsq.ll53 ; SI-UNSAFE-DAG: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[MUL]]
54 ; SI-UNSAFE-DAG: v_mul_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[RCP]]
100 ; SI-UNSAFE: v_rcp_f64_e32 [[RCP:v\[[0-9]+:[0-9]+\]]], [[VAL]]
101 ; SI-UNSAFE: v_fma_f64 {{v\[[0-9]+:[0-9]+\]}}, -{{v\[[0-9]+:[0-9]+\]}}, [[RCP]], 1.0
H A Dfdiv.f16.ll190 ; GFX8_9_10: v_rcp_f16_e32 [[RCP:v[0-9]+]], [[RHS]]
191 ; GFX8_9_10: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[LHS]], [[RCP]]
212 ; GFX8_9_10: v_rcp_f16_e32 [[RCP:v[0-9]+]], [[RHS]]
213 ; GFX8_9_10: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[LHS]], [[RCP]]
H A Dselect-fabs-fneg-extract.ll807 ; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[X]]
808 ; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], -2.0, [[RCP]], vcc
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.h416 RCP, enumerator
H A DAMDGPUCodeGenPrepare.cpp954 Value *RCP = Builder.CreateCall(RcpDecl, { FB }); in expandDivRem24Impl() local
955 Value *FQM = Builder.CreateFMul(FA, RCP); in expandDivRem24Impl()
H A DAMDGPUISelLowering.cpp512 case AMDGPUISD::RCP: in fnegFoldsIntoOp()
1625 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb)); in LowerDIVREM24()
1738 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1); in LowerUDIVREM64()
3850 case AMDGPUISD::RCP: in performFNegCombine()
4136 case AMDGPUISD::RCP: in PerformDAGCombine()
4312 NODE_NAME_CASE(RCP) in getTargetNodeName()
4450 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand); in getRecipEstimate()
4732 case AMDGPUISD::RCP: in isKnownNeverNaNForTargetNode()
H A DAMDGPUInstrInfo.td112 def AMDGPUrcp_impl : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
H A DAMDGPULegalizerInfo.cpp3788 auto RCP = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {ResTy}, false) in legalizeFastUnsafeFDIV() local
3791 B.buildFMul(Res, LHS, RCP, Flags); in legalizeFastUnsafeFDIV()
3852 auto RCP = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S32}, false) in legalizeFDIV16() local
3856 auto QUOT = B.buildFMul(S32, LHSExt, RCP, Flags); in legalizeFDIV16()
4072 auto RCP = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S32}, false) in legalizeFDIVFastIntrin() local
4076 auto Mul1 = B.buildFMul(S32, LHS, RCP, Flags); in legalizeFDIVFastIntrin()
H A DSIISelLowering.cpp6828 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
8831 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS); in lowerFastUnsafeFDIV()
8838 return DAG.getNode(AMDGPUISD::RCP, SL, VT, FNegRHS); in lowerFastUnsafeFDIV()
8844 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS); in lowerFastUnsafeFDIV()
8864 SDValue R = DAG.getNode(AMDGPUISD::RCP, SL, VT, Y); in lowerFastUnsafeFDIV64()
8930 SDValue RcpSrc1 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, CvtSrc1); in LowerFDIV16()
8966 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1); in lowerFDIV_FAST()
9011 SDValue ApproxRcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, in LowerFDIV32()
9118 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0); in LowerFDIV64()
10033 case AMDGPUISD::RCP: in isCanonicalized()
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H A DAMDGPUISelDAGToDAG.cpp179 case AMDGPUISD::RCP: in fp16SrcZerosHighBits()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrSSE.td3044 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SchedWriteFRcp, HasAVX>,