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Searched refs:RB (Results 1 – 25 of 56) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrSPE.td19 bits<5> RB;
25 let Inst{16-20} = RB;
32 let RB = 0;
46 bits<5> RB;
51 let Inst{16-20} = RB;
60 bits<5> RB;
66 let Inst{16-20} = RB;
73 let RB = 0;
87 bits<5> RB;
94 let Inst{16-20} = RB;
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H A DPPCExpandAtomicPseudoInsts.cpp156 Register RB = MI.getOperand(3).getReg(); in expandAtomicRMW128() local
162 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicRMW128()
204 BuildMI(CurrentMBB, DL, SC).addReg(Scratch).addReg(RA).addReg(RB); in expandAtomicRMW128()
233 Register RB = MI.getOperand(3).getReg(); in expandAtomicCmpSwap128() local
266 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicCmpSwap128()
286 BuildMI(CurrentMBB, DL, SC).addReg(Scratch).addReg(RA).addReg(RB); in expandAtomicCmpSwap128()
295 BuildMI(CurrentMBB, DL, SC).addReg(Old).addReg(RA).addReg(RB); in expandAtomicCmpSwap128()
H A DPPCInstrHTM.td106 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
107 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>;
112 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
113 (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;
H A DPPCInstrFormats.td564 bits<5> RB;
580 bits<5> RB;
614 bits<5> RB;
952 bits<5> RB;
971 bits<5> RB;
1216 bits<5> RB;
1414 bits<5> RB;
1742 bits<5> RB;
1759 let RB = 0;
1800 bits<5> RB;
[all …]
/llvm-project-15.0.7/compiler-rt/lib/sanitizer_common/tests/
H A Dsanitizer_ring_buffer_test.cpp36 RingBuffer<T> *RB; in TestRB() local
39 RB = RingBuffer<T>::New(Size); in TestRB()
40 EXPECT_EQ(RB->size(), Size); in TestRB()
41 RB->Delete(); in TestRB()
44 RB = RingBuffer<T>::New(4); in TestRB()
45 EXPECT_EQ(RB->size(), 4U); in TestRB()
50 EXPECT_EQ((int64_t)(*RB)[3], (int64_t)a3); in TestRB()
52 RB->push(T(1)); EXPECT_RING_BUFFER(1, 0, 0, 0); in TestRB()
53 RB->push(T(2)); EXPECT_RING_BUFFER(2, 1, 0, 0); in TestRB()
54 RB->push(T(3)); EXPECT_RING_BUFFER(3, 2, 1, 0); in TestRB()
[all …]
/llvm-project-15.0.7/clang/lib/Rewrite/
H A DHTMLRewrite.cpp62 RB.InsertTextAfter(B, StartTag); in HighlightRange()
63 RB.InsertTextBefore(E, EndTag); in HighlightRange()
96 RB.InsertTextAfter(i, StartTag); in HighlightRange()
133 RB.ReplaceText(FilePos, 1, "<hr>"); in EscapeText()
142 RB.ReplaceText(FilePos, 1, in EscapeText()
151 RB.ReplaceText(FilePos, 1, "&lt;"); in EscapeText()
156 RB.ReplaceText(FilePos, 1, "&gt;"); in EscapeText()
220 RB.InsertTextBefore(B, OS.str()); in AddLineNumber()
222 RB.InsertTextBefore(B, OS.str()); in AddLineNumber()
223 RB.InsertTextBefore(E, "</td></tr>"); in AddLineNumber()
[all …]
H A DRewriter.cpp162 const RewriteBuffer &RB = I->second; in getRangeSize() local
163 EndOff = RB.getMappedOffset(EndOff, opts.IncludeInsertsAtEndOfRange); in getRangeSize()
164 StartOff = RB.getMappedOffset(StartOff, !opts.IncludeInsertsAtBeginOfRange); in getRangeSize()
213 const RewriteBuffer &RB = I->second; in getRewrittenText() local
214 EndOff = RB.getMappedOffset(EndOff, true); in getRewrittenText()
215 StartOff = RB.getMappedOffset(StartOff); in getRewrittenText()
223 RewriteBuffer::iterator Start = RB.begin(); in getRewrittenText()
399 RewriteBuffer &RB = getEditBuffer(FID); in IncreaseIndentation() local
407 RB.InsertText(offs, indent, /*InsertAfter=*/false); in IncreaseIndentation()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRDFRegisters.h118 bool alias(RegisterRef RA, RegisterRef RB) const { in alias()
120 return !isRegMaskId(RB.Reg) ? aliasRR(RA, RB) : aliasRM(RA, RB); in alias()
121 return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB); in alias()
163 bool aliasRR(RegisterRef RA, RegisterRef RB) const;
182 static bool isCoverOf(RegisterRef RA, RegisterRef RB, in isCoverOf()
184 return RegisterAggr(PRI).insert(RA).hasCoverOf(RB); in isCoverOf()
/llvm-project-15.0.7/clang/test/Layout/
H A Dms-x86-alias-avoidance-padding.cpp254 struct RB { char c; }; struct
258 struct RX0 : RB, RA {};
259 struct RX1 : RA, RB {};
261 struct RX3 : RA { RB a; };
263 struct RX5 { RA a; RB b; };
264 struct RX6 : virtual RV { RB a; };
/llvm-project-15.0.7/clang/lib/Frontend/Rewrite/
H A DRewriteMacros.cpp94 RewriteBuffer &RB = Rewrite.getEditBuffer(SM.getMainFileID()); in RewriteMacrosInInput() local
133 RB.InsertTextAfter(SM.getFileOffset(RawTok.getLocation()), "//"); in RewriteMacrosInInput()
139 RB.InsertTextAfter(SM.getFileOffset(RawTok.getLocation()), "//"); in RewriteMacrosInInput()
169 RB.InsertTextAfter(RawOffs, &" /*"[HasSpace]); in RewriteMacrosInInput()
187 RB.InsertTextBefore(EndPos, "*/"); in RewriteMacrosInInput()
203 RB.InsertTextBefore(InsertPos, Expansion); in RewriteMacrosInInput()
/llvm-project-15.0.7/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_ring_buffer.h27 RingBuffer *RB = reinterpret_cast<RingBuffer*>(Ptr); in New() local
29 RB->last_ = RB->next_ = reinterpret_cast<T*>(End - sizeof(T)); in New()
30 return RB; in New()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dcfi-inserter-basic-block-sections-callee-save-registers.ll8 ; SECTIONS_CFI-NEXT: .cfi_offset [[RB:%r.+]], -48
16 ; SECTIONS_CFI-NEXT: .cfi_offset [[RB]], -48
24 ; SECTIONS_CFI-NEXT: .cfi_offset [[RB]], -48
/llvm-project-15.0.7/clang/lib/StaticAnalyzer/Checkers/
H A DMacOSXAPIChecker.cpp77 const MemRegion *RB = R->getBaseRegion(); in CheckDispatchOnce() local
78 const MemSpaceRegion *RS = RB->getMemorySpace(); in CheckDispatchOnce()
96 if (const VarRegion *VR = dyn_cast<VarRegion>(RB)) { in CheckDispatchOnce()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCSEInfo.cpp348 GISelInstProfileBuilder::addNodeIDRegType(const RegisterBank *RB) const { in addNodeIDRegType()
349 ID.AddPointer(RB); in addNodeIDRegType()
391 if (const auto *RB = RCOrRB.dyn_cast<const RegisterBank *>()) in addNodeIDReg() local
392 addNodeIDRegType(RB); in addNodeIDReg()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRDFRegisters.cpp136 bool PhysicalRegisterInfo::aliasRR(RegisterRef RA, RegisterRef RB) const { in aliasRR()
138 assert(Register::isPhysicalRegister(RB.Reg)); in aliasRR()
141 MCRegUnitMaskIterator UMB(RB.Reg, &TRI); in aliasRR()
152 if (PB.second.any() && (PB.second & RB.Mask).none()) { in aliasRR()
H A DRegisterBankInfo.cpp90 if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>()) in getRegBank() local
91 return RB; in getRegBank()
137 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>(); in constrainGenericRegister() local
139 if (RB && !RB->covers(RC)) in constrainGenericRegister()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp171 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
181 if (RB.getID() == X86::VECRRegBankID) { in getRegClass()
398 const RegisterBank &RB, in getLoadStoreOp() argument
407 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
410 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
413 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
415 if (X86::VECRRegBankID == RB.getID()) in getLoadStoreOp()
423 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
425 if (X86::VECRRegBankID == RB.getID()) in getLoadStoreOp()
512 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp516 if (RB.getID() == AArch64::GPRRegBankID) { in getRegClassForTypeOnBank()
528 if (RB.getID() == AArch64::FPRRegBankID) { in getRegClassForTypeOnBank()
552 unsigned RegBankID = RB.getID(); in getMinClassForRegBank()
615 switch (RB.getID()) { in getMinSizeForRegBank()
2856 MRI.setRegBank(NewDst, RB); in select()
4005 if (RB.getID() != AArch64::GPRRegBankID) in selectMergeValues()
4400 if (RB.getID() == AArch64::GPRRegBankID) { in getInsertVecEltOpInfo()
5208 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert() argument
5221 if (RB.getID() == AArch64::FPRRegBankID) { in emitLaneInsert()
6814 if (RB != DstRB) { in fixupPHIOpBanks()
[all …]
H A DAArch64RegisterBankInfo.cpp100 #define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB) \ in AArch64RegisterBankInfo() argument
103 checkPartialMap(PartialMappingIdx::Idx, ValStartIdx, ValLength, RB) && \ in AArch64RegisterBankInfo()
512 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints() local
513 if (RB == &AArch64::FPRRegBank) in hasFPConstraints()
515 if (RB == &AArch64::GPRRegBank) in hasFPConstraints()
H A DAArch64RegisterBankInfo.h65 unsigned ValLength, const RegisterBank &RB);
/llvm-project-15.0.7/clang/include/clang/Rewrite/Core/
H A DHTMLRewrite.h47 void HighlightRange(RewriteBuffer &RB, unsigned B, unsigned E,
/llvm-project-15.0.7/clang/lib/Frontend/
H A DPrecompiledPreamble.cpp636 for (const auto &RB : PreprocessorOpts.RemappedFileBuffers) { in CanReuse() local
638 PreambleFileHash::createForMemoryBuffer(RB.second->getMemBufferRef()); in CanReuse()
640 if (moveOnNoError(VFS.status(RB.first), Status)) in CanReuse()
643 OverridenFileBuffers[RB.first] = PreambleHash; in CanReuse()
645 llvm::SmallString<128> MappedPath(RB.first); in CanReuse()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dmisched-fusion-addr.ll28 ; CHECK: adrp [[RB:x[0-9]+]], var_8bit
29 ; CHECK-NEXT: ldrb {{w[0-9]+}}, [[[RB]], {{#?}}:lo12:var_8bit]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Dstack-access.ll122 ; CHECK-DAG: ldr [[RB:r[0-9]+]], .LCPI7_3
123 ; CHECK-DAG: add [[RB]], sp
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.cpp253 MachineBasicBlock::iterator RB = Begin; in runOnMachineFunction() local
254 while (RB != End && HII->isSchedulingBoundary(*RB, &MB, MF)) in runOnMachineFunction()
255 ++RB; in runOnMachineFunction()
258 MachineBasicBlock::iterator RE = RB; in runOnMachineFunction()
265 if (RB != End) in runOnMachineFunction()
266 Packetizer.PacketizeMIs(&MB, RB, RE); in runOnMachineFunction()

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