155                                const RegisterBank &RB,
514 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB,  in getRegClassForTypeOnBank()  argument
516   if (RB.getID() == AArch64::GPRRegBankID) {  in getRegClassForTypeOnBank()
528   if (RB.getID() == AArch64::FPRRegBankID) {  in getRegClassForTypeOnBank()
550 getMinClassForRegBank(const RegisterBank &RB, unsigned SizeInBits,  in getMinClassForRegBank()  argument
552   unsigned RegBankID = RB.getID();  in getMinClassForRegBank()
614 static unsigned getMinSizeForRegBank(const RegisterBank &RB) {  in getMinSizeForRegBank()  argument
615   switch (RB.getID()) {  in getMinSizeForRegBank()
2364         const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();  in select()  local
2365         DefRC = getRegClassForTypeOnBank(DefTy, RB);  in select()
2521     const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);  in select()  local
2532       if (RB.getID() != AArch64::FPRRegBankID) {  in select()
2534                           << " constant on bank: " << RB  in select()
2554       if (RB.getID() != AArch64::GPRRegBankID) {  in select()
2556                           << " constant on bank: " << RB  in select()
2563       const TargetRegisterClass &FPRRC = *getRegClassForTypeOnBank(DefTy, RB);  in select()
2826     const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI);  in select()  local
2833       auto *RC = getRegClassForTypeOnBank(MemTy, RB);  in select()
2846       if (RB.getID() == AArch64::FPRRegBankID) {  in select()
2849         auto *RC = getRegClassForTypeOnBank(MemTy, RB);  in select()
2856         MRI.setRegBank(NewDst, RB);  in select()
2863         auto SubRegRC = getRegClassForTypeOnBank(MRI.getType(OldDst), RB);  in select()
2874           selectLoadStoreUIOp(I.getOpcode(), RB.getID(), MemSizeInBits);  in select()
2950     const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);  in select()  local
2952     if (RB.getID() != AArch64::GPRRegBankID) {  in select()
2953       LLVM_DEBUG(dbgs() << "G_[SU]MULH on bank: " << RB << ", expected: GPR\n");  in select()
3009     const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);  in select()  local
3011     const unsigned NewOpc = selectBinaryOp(I.getOpcode(), RB.getID(), OpSize);  in select()
3978   const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);  in selectMergeValues()  local
3992         emitLaneInsert(None, Tmp.getReg(0), Src1Reg, /* LaneIdx */ 0, RB, MIB);  in selectMergeValues()
3996                                           Src2Reg, /* LaneIdx */ 1, RB, MIB);  in selectMergeValues()
4005   if (RB.getID() != AArch64::GPRRegBankID)  in selectMergeValues()
4398 getInsertVecEltOpInfo(const RegisterBank &RB, unsigned EltSize) {  in getInsertVecEltOpInfo()  argument
4400   if (RB.getID() == AArch64::GPRRegBankID) {  in getInsertVecEltOpInfo()
5208     unsigned LaneIdx, const RegisterBank &RB,  in emitLaneInsert()  argument
5219   unsigned Opc = getInsertVecEltOpInfo(RB, EltSize).first;  in emitLaneInsert()
5221   if (RB.getID() == AArch64::FPRRegBankID) {  in emitLaneInsert()
5502   const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);  in selectBuildVector()  local
5520     PrevMI = &*emitLaneInsert(None, DstVec, I.getOperand(i).getReg(), i - 1, RB,  in selectBuildVector()
6813     const RegisterBank *RB = MRI.getRegBankOrNull(OpReg);  in fixupPHIOpBanks()  local
6814     if (RB != DstRB) {  in fixupPHIOpBanks()
6875       const RegisterBank *RB = MRI.getRegBankOrNull(MO.getReg());  in processPHIs()  local
6877       if (!RB)  in processPHIs()
6880       if (RB->getID() == AArch64::GPRRegBankID)  in processPHIs()