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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A Dbitcast.ll51 ; BIGENDIAN: addv.h [[R4:\$w[0-9]+]], [[R3]], [[R3]]
99 ; BIGENDIAN: addv.w [[R4:\$w[0-9]+]], [[R3]], [[R3]]
124 ; BIGENDIAN: fadd.w [[R4:\$w[0-9]+]], [[R3]], [[R3]]
149 ; BIGENDIAN: shf.w [[R3:\$w[0-9]+]], [[R3]], 177
150 ; BIGENDIAN: addv.d [[R4:\$w[0-9]+]], [[R3]], [[R3]]
175 ; BIGENDIAN: shf.w [[R3:\$w[0-9]+]], [[R3]], 177
176 ; BIGENDIAN: fadd.d [[R4:\$w[0-9]+]], [[R3]], [[R3]]
273 ; BIGENDIAN: addv.w [[R4:\$w[0-9]+]], [[R3]], [[R3]]
298 ; BIGENDIAN: fadd.w [[R4:\$w[0-9]+]], [[R3]], [[R3]]
877 ; BIGENDIAN: shf.w [[R3:\$w[0-9]+]], [[R3]], 177
[all …]
H A Darithmetic_float.ll14 ; CHECK-DAG: st.w [[R3]], 0($4)
30 ; CHECK-DAG: st.d [[R3]], 0($4)
46 ; CHECK-DAG: st.w [[R3]], 0($4)
62 ; CHECK-DAG: st.d [[R3]], 0($4)
78 ; CHECK-DAG: st.w [[R3]], 0($4)
94 ; CHECK-DAG: st.d [[R3]], 0($4)
192 ; CHECK-DAG: st.w [[R3]], 0($4)
208 ; CHECK-DAG: st.d [[R3]], 0($4)
222 ; CHECK-DAG: st.w [[R3]], 0($4)
236 ; CHECK-DAG: st.d [[R3]], 0($4)
[all …]
H A Dshuffle.ll14 ; CHECK-DAG: st.b [[R3]], 0($4)
27 ; CHECK-DAG: st.b [[R3]], 0($4)
43 ; CHECK-DAG: st.b [[R3]], 0($4)
62 ; CHECK-DAG: st.b [[R3]], 0($4)
75 ; CHECK-DAG: st.b [[R3]], 0($4)
90 ; CHECK-DAG: st.h [[R3]], 0($4)
103 ; CHECK-DAG: st.h [[R3]], 0($4)
119 ; CHECK-DAG: st.h [[R3]], 0($4)
138 ; CHECK-DAG: st.h [[R3]], 0($4)
151 ; CHECK-DAG: st.h [[R3]], 0($4)
[all …]
H A Dcompare.ll15 ; CHECK-DAG: st.b [[R3]], 0($4)
32 ; CHECK-DAG: st.h [[R3]], 0($4)
49 ; CHECK-DAG: st.w [[R3]], 0($4)
66 ; CHECK-DAG: st.d [[R3]], 0($4)
355 ; CHECK-DAG: xori.b [[R3]], [[R3]], 255
375 ; TODO: This should be an 'xori.b [[R3]], [[R3]], 255' but thats an optimisation issue
377 ; CHECK-DAG: xor.v [[R3]], [[R3]], [[R4]]
397 ; TODO: This should be an 'xori.b [[R3]], [[R3]], 255' but thats an optimisation issue
399 ; CHECK-DAG: xor.v [[R3]], [[R3]], [[R4]]
419 ; TODO: This should be an 'xori.b [[R3]], [[R3]], 255' but thats an optimisation issue
[all …]
H A Dcompare_float.ll52 ; CHECK-DAG: st.w [[R3]], 0($4)
69 ; CHECK-DAG: st.d [[R3]], 0($4)
86 ; CHECK-DAG: st.w [[R3]], 0($4)
103 ; CHECK-DAG: st.d [[R3]], 0($4)
120 ; CHECK-DAG: st.w [[R3]], 0($4)
137 ; CHECK-DAG: st.d [[R3]], 0($4)
154 ; CHECK-DAG: st.w [[R3]], 0($4)
171 ; CHECK-DAG: st.d [[R3]], 0($4)
188 ; CHECK-DAG: st.w [[R3]], 0($4)
205 ; CHECK-DAG: st.d [[R3]], 0($4)
[all …]
H A Dshift_constant_pool.ll33 ; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_bclr_w_test_const_vec_res)($[[R1]])
38 ; ALL: st.w $w0, 0($[[R3]])
61 ; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_bneg_w_test_const_vec_res)($[[R1]])
66 ; ALL: st.w $w0, 0($[[R3]])
89 ; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_bset_w_test_const_vec_res)($[[R1]])
94 ; ALL: st.w $w0, 0($[[R3]])
116 ; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_sll_w_test_const_vec_res)($[[R1]])
121 ; ALL: st.w $w0, 0($[[R3]])
143 ; MIPS32: lw $[[R3:[0-9]+]], %got(llvm_mips_sra_w_test_const_vec_res)($[[R1]])
148 ; ALL: st.w $w0, 0($[[R3]])
[all …]
H A D3r-a.ll34 ; CHECK-DAG: st.b [[WD]], 0([[R3]])
59 ; CHECK-DAG: st.h [[WD]], 0([[R3]])
84 ; CHECK-DAG: st.w [[WD]], 0([[R3]])
109 ; CHECK-DAG: st.d [[WD]], 0([[R3]])
134 ; CHECK-DAG: st.b [[WD]], 0([[R3]])
159 ; CHECK-DAG: st.h [[WD]], 0([[R3]])
184 ; CHECK-DAG: st.w [[WD]], 0([[R3]])
209 ; CHECK-DAG: st.d [[WD]], 0([[R3]])
234 ; CHECK-DAG: st.b [[WD]], 0([[R3]])
259 ; CHECK-DAG: st.h [[WD]], 0([[R3]])
[all …]
H A D3r_splat.ll25 ; MIPS32-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])
26 ; MIPS32-DAG: splat.b [[R4:\$w[0-9]+]], [[R3]][$4]
46 ; MIPS32-DAG: ld.h [[R3:\$w[0-9]+]], 0([[R1]])
47 ; MIPS32-DAG: splat.h [[R4:\$w[0-9]+]], [[R3]][$4]
67 ; MIPS32-DAG: ld.w [[R3:\$w[0-9]+]], 0([[R1]])
68 ; MIPS32-DAG: splat.w [[R4:\$w[0-9]+]], [[R3]][$4]
88 ; MIPS32-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]])
89 ; MIPS32-DAG: splat.d [[R4:\$w[0-9]+]], [[R3]][$4]
103 ; MIPS32-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]])
104 ; MIPS32-DAG: splat.d [[R4:\$w[0-9]+]], [[R3]][$4]
[all …]
H A Dbmzi_bmnzi.ll23 ; CHECK: ld.b [[R3:\$w[0-9]+]], 0([[R2]])
26 ; CHECK: binsli.b [[R5]], [[R3]], 3
27 ; CHECK: binsri.b [[R5]], [[R3]], 3
28 ; CHECK: bmnzi.b [[R4]], [[R3]], 170
46 ; CHECK: ld.b [[R3:\$w[0-9]+]], 0([[R2]])
49 ; CHECK: binsli.b [[R5]], [[R3]], 3
50 ; CHECK: binsri.b [[R5]], [[R3]], 3
52 ; CHECK: bmnzi.b [[R4]], [[R3]], 170
H A Delm_insv.ll98 ; MIPS32-DAG: ld.w [[R3:\$w[0-9]+]],
100 ; MIPS32-DAG: insert.w [[R3]][2], [[R1]]
101 ; MIPS32-DAG: insert.w [[R3]][3], [[R2]]
103 ; MIPS32-DAG: st.w [[R3]],
129 ; MIPS-ANY-DAG: insve.b [[R3]][1], [[R4]][0]
130 ; MIPS-ANY-DAG: st.b [[R3]],
155 ; MIPS-ANY-DAG: insve.h [[R3]][1], [[R4]][0]
156 ; MIPS-ANY-DAG: st.h [[R3]],
181 ; MIPS-ANY-DAG: insve.w [[R3]][1], [[R4]][0]
182 ; MIPS-ANY-DAG: st.w [[R3]],
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cconv/
H A Darguments.ll70 ; O32-DAG: sb [[R3]], 5([[R1]])
73 ; O32-DAG: sb [[R3]], 6([[R1]])
76 ; O32-DAG: sb [[R3]], 7([[R1]])
79 ; O32-DAG: sb [[R3]], 8([[R1]])
86 ; O32-DAG: sb [[R3]], 9([[R1]])
88 ; NEW-DAG: sb [[R3]], 9([[R1]])
90 ; O32-DAG: sb [[R3]], 10([[R1]])
144 ; O32-DAG: sb [[R3]], 2([[R1]])
147 ; O32-DAG: sb [[R3]], 3([[R1]])
150 ; O32-DAG: sb [[R3]], 4([[R1]])
[all …]
H A Darguments-float.ll68 ; O32-DAG: sw [[R3]], 24([[R2]])
74 ; O32-DAG: sw [[R3]], 32([[R2]])
80 ; O32-DAG: sw [[R3]], 40([[R2]])
86 ; O32-DAG: sw [[R3]], 48([[R2]])
92 ; O32-DAG: sw [[R3]], 56([[R2]])
99 ; O32-DAG: sw [[R3]], 64([[R2]])
150 ; O32-DAG: sw [[R3]], 20([[R2]])
154 ; O32-DAG: sw [[R3]], 24([[R2]])
158 ; O32-DAG: sw [[R3]], 28([[R2]])
162 ; O32-DAG: sw [[R3]], 32([[R2]])
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Dldm-stm-base-materialization.ll16 ; CHECK-NEXT: ldm r[[NLB]]!, {r[[R1:[0-9]]], r[[R2:[0-9]]], r[[R3:[0-9]]]}
17 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]]}
18 ; CHECK-NEXT: ldm r[[NLB]]!, {r[[R1:[0-9]]], r[[R2:[0-9]]], r[[R3:[0-9]]]}
19 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]]}
38 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]]}
40 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]], r[[R4]]}
59 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]], r[[R4]]}
61 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]], r[[R4]]}
80 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]]}
82 ; CHECK-NEXT: stm r[[NSB]]!, {r[[R1]], r[[R2]], r[[R3]]}
[all …]
H A Dldm-stm-base-materialization-thumb2.ll18 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]], {[[R1]], [[R2]], [[R3]], [[R4]], [[R5]], [[R6]]}
36 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]]}
37 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]]!, {[[R1]], [[R2]], [[R3]]}
38 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-…
39 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
57 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0…
58 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
59 ; CHECK-NEXT: ldm{{(\.w)?}} [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-…
60 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
79 ; CHECK-NEXT: stm{{(\.w)?}} [[SB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dldm-stm-base-materialization.ll18 ; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]], [[R5]], [[R6]]}
36 ; CHECK-NEXT: ldm [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]]}
37 ; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]]}
38 ; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]}
39 ; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
57 ; CHECK-NEXT: ldm [[NLB]]!, {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]}
58 ; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
59 ; CHECK-NEXT: ldm [[NLB]], {[[R1:[rl0-9]+]], [[R2:[rl0-9]+]], [[R3:[rl0-9]+]], [[R4:[rl0-9]+]]}
60 ; CHECK-NEXT: stm [[NSB]], {[[R1]], [[R2]], [[R3]], [[R4]]}
79 ; CHECK-NEXT: stm [[NSB]]!, {[[R1]], [[R2]], [[R3]], [[R4]]}
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SCCP/
H A Dub-shift.ll8 ; CHECK-NEXT: [[R3:%.*]] = shl i64 -1, 4294967298
9 ; CHECK-NEXT: store i64 [[R3]], i64* [[P]]
28 ; CHECK-NEXT: [[R3:%.*]] = shl i65 1, -18446744073709551615
29 ; CHECK-NEXT: store i65 [[R3]], i65* [[P]]
48 ; CHECK-NEXT: [[R3:%.*]] = shl i256 1, 18446744073709551619
49 ; CHECK-NEXT: store i256 [[R3]], i256* [[P]]
68 ; CHECK-NEXT: [[R3:%.*]] = shl i511 -3, 1208925819614629174706180
69 ; CHECK-NEXT: store i511 [[R3]], i511* [[P]]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dbiggot.ll19 ; O32: addu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
20 ; O32: lw ${{[0-9]+}}, %call_lo(foo0)($[[R3]])
26 ; N64-DAG: daddu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
28 ; N64-DAG: ld ${{[0-9]+}}, %call_lo(foo0)($[[R3]])
43 ; O32: addu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
44 ; O32: lw ${{[0-9]+}}, %call_lo(memcpy)($[[R3]])
48 ; N64: daddu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
49 ; N64: ld ${{[0-9]+}}, %call_lo(memcpy)($[[R3]])
H A Dmno-ldc1-sdc1.ll86 ; 32R1-LE-STATIC-DAG: mtc1 $[[R3]], $f1
93 ; 32R2-LE-STATIC-DAG: mthc1 $[[R3]], $f0
100 ; 32R6-LE-STATIC-DAG: mthc1 $[[R3]], $f0
127 ; MM: ldc1 $f0, 0($[[R3]])
171 ; 32R1-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]])
178 ; 32R2-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]])
185 ; 32R6-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]])
212 ; MM: sdc1 $f12, 0($[[R3]])
273 ; MM-MNO-LE-PIC: mthc1 $[[R3]], $f0
274 ; MM-MNO-BE-PIC: mtc1 $[[R3]], $f0
[all …]
H A Dbswap.ll28 ; MIPS16-DAG: sll $[[R3:[0-9]+]], $4, 24
34 ; MIPS16-DAG: or $[[R3]], $[[R7]]
35 ; MIPS16-DAG: or $[[R3]], $[[R1]]
63 ; MIPS16-DAG: sll $[[R3:[0-9]+]], $5, 24
69 ; MIPS16-DAG: or $[[R3]], $[[R2]]
70 ; MIPS16-DAG: or $[[R3]], $[[R1]]
74 ; MIPS16-DAG: sll $[[R3:[0-9]+]], $4, 24
78 ; MIPS16-DAG: or $[[R3]], $[[R2]]
79 ; MIPS16-DAG: or $[[R3]], $[[R1]]
H A Dmicromips-lwc1-swc1.ll16 ; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]])
17 ; MM32: lwc1 $f0, 0($[[R3]])
29 ; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]])
30 ; MM32: swc1 $f12, 0($[[R3]])
H A Dglobal-address.ll43 ; STATIC-N64: lui $[[R3:[0-9]+]], %highest(g1)
44 ; STATIC-N64: daddiu $[[R3]], $[[R3]], %higher(g1)
45 ; STATIC-N64: daddiu $[[R3]], $[[R3]], %hi(g1)
46 ; STATIC-N64: lw ${{[0-9]+}}, %lo(g1)($[[R3]])
H A Dblockaddr.ll30 ; STATIC-O32: lui $[[R3:[0-9]+]], %hi($tmp[[T3:[0-9]+]])
31 ; STATIC-O32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]])
40 ; STATIC-N32: lui $[[R3:[0-9]+]], %hi(.Ltmp[[T3:[0-9]+]])
41 ; STATIC-N32: addiu ${{[0-9]+}}, $[[R3]], %lo(.Ltmp[[T3]])
51 ; STATIC-N64: daddiu $[[R3:[0-9]]], $[[R2]], %hi(.Ltmp[[L0]])
52 ; STATIC-N64: dsll $[[R4:[0-9]]], $[[R3]], 16
59 ; STATIC-MIPS16: addu $[[R3:[0-9]+]], $[[R1]], $[[R2]]
/llvm-project-15.0.7/compiler-rt/lib/builtins/hexagon/
H A Dfastmath2_ldlib_asm.S54 #define mantb R3:2
55 #define lmantb R3:2
64 #define zero R3:2
153 #define mantb R3:2
154 #define lmantb R3:2
163 #define zero R3:2
258 #define mantbh R3
259 #define mantb R3:2
H A Dfastmath_dlib_asm.S61 #define mantexpb R3:2
62 #define lmantb R3:2
74 #define minus R3:2
196 #define mantexpb R3:2
197 #define lmantb R3:2
209 #define minus R3:2
325 #define mantbh R3
326 #define mantexpb R3:2
336 #define minus1 R3:2
/llvm-project-15.0.7/llvm/test/CodeGen/SPARC/
H A Dblockaddr.ll36 ; abs64: add [[R2]], %hm([[BLK]]), [[R3:%[gilo][0-7]]]
37 ; abs64: sllx [[R3]], 32, [[R4:%[gilo][0-7]]]
47 ; v8pic32: sethi %hi([[BLK:.+]]), [[R3:%[gilo][0-7]]]
48 ; v8pic32: add [[R3]], %lo([[BLK]]), %[[R4:[gilo][0-7]]]
58 ; v9pic32: sethi %hi([[BLK:.+]]), [[R3:%[gilo][0-7]]]
59 ; v9pic32: add [[R3]], %lo([[BLK]]), %[[R4:[gilo][0-7]]]

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