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Searched refs:R16 (Results 1 – 25 of 46) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AVR/
H A Dsext.ll3 ; sext R17:R16, R13
18 ; sext R17:R16, R16
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dfunnel-shift2.ll6 ; CHECK: r[[R17:[0-9]+]]:[[R16:[0-9]+]] = combine
9 ; CHECK: r[[R1]]:[[R0]] |= lsr(r[[R17]]:[[R16]],#1)
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td52 def R16 : AVRReg<16, "r16">, DwarfRegNum<[16]>;
87 def R17R16 : AVRReg<16, "r17:r16", [R16, R17]>, DwarfRegNum<[16]>;
103 def R16R15 : AVRReg<15, "r16:r15", [R15, R16]>, DwarfRegNum<[15]>;
121 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
137 R28, R29, R17, R16)>;
141 (add R23, R22, R21, R20, R19, R18, R17, R16)>;
/llvm-project-15.0.7/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYInstPrinter.cpp247 printRegName(O, CSKY::R16); in printRegisterList()
253 printRegName(O, CSKY::R16 + Offset); in printRegisterList()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h81 case Lanai::R16: in getLanaiRegisterNumbering()
/llvm-project-15.0.7/llvm/test/Transforms/LowerTypeTests/
H A Dsimple.ll66 ; CHECK: [[R16:%[^ ]*]] = phi i1 [ false, {{%[^ ]*}} ], [ [[R11]], {{%[^ ]*}} ]
72 ; CHECK: ret i1 [[R16]]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td46 (add R3, R9, R12, R13, R14, R16, R17,
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp121 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
130 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
H A DHexagonFrameLowering.h93 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 }, in getCalleeSavedSpillSlots()
H A DHexagonRegisterInfo.td145 def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>;
539 (add R23, R22, R21, R20, R19, R18, R17, R16,
643 : CalleeSavedRegs<(add R16, R17, R18, R19, R20, R21, R22, R23,
/llvm-project-15.0.7/llvm/unittests/IR/
H A DConstantRangeTest.cpp2431 ConstantRange R16(APInt(8, 16)); in TEST_F() local
2433 EXPECT_EQ(*R16.binaryAnd(R16).getSingleElement(), APInt(8, 16)); in TEST_F()
2434 EXPECT_EQ(*R16.binaryAnd(R20).getSingleElement(), APInt(8, 16 & 20)); in TEST_F()
2463 ConstantRange R16(APInt(8, 16)); in TEST_F() local
2465 EXPECT_EQ(*R16.binaryOr(R16).getSingleElement(), APInt(8, 16)); in TEST_F()
2466 EXPECT_EQ(*R16.binaryOr(R20).getSingleElement(), APInt(8, 16 | 20)); in TEST_F()
2501 ConstantRange R16(APInt(8, 16)); in TEST_F() local
2503 EXPECT_EQ(*R16.binaryXor(R16).getSingleElement(), APInt(8, 0)); in TEST_F()
2504 EXPECT_EQ(*R16.binaryXor(R20).getSingleElement(), APInt(8, 16 ^ 20)); in TEST_F()
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-multi-reduction-outer-lowering.mlir157 // CHECK: %[[R16:.+]] = arith.addi %[[V17]], %[[R15]] : vector<6xi32>
159 // CHECK: %[[R17:.+]] = arith.addi %[[V18]], %[[R16]] : vector<6xi32>
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/vect/
H A Dsetcc-v32.ll182 ; CHECK: [[R16:r[0-9:]+]] = vsxthw(r1)
183 ; CHECK: [[P16:p[0-3]+]] = vcmpw.gtu([[R16]],[[L16]])
/llvm-project-15.0.7/llvm/lib/Target/CSKY/AsmParser/
H A DCSKYAsmParser.cpp346 if (from != CSKY::R4 && from != CSKY::R15 && from != CSKY::R16 && in isLegalRegList()
352 if (from != CSKY::R4 && from != CSKY::R16) in isLegalRegList()
357 else if (from == CSKY::R16 && to > CSKY::R16 && to < CSKY::R18) in isLegalRegList()
590 else if (ListFrom == CSKY::R16) in getListValue()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp158 Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.cpp68 markSuperRegs(Reserved, CSKY::R16 + i); // R16 - R25 in getReservedRegs()
H A DCSKYRegisterInfo.td68 def R16 : CSKYReg<16, "r16", ["l8"]>, DwarfRegNum<[16]>;
/llvm-project-15.0.7/llvm/test/TableGen/
H A DTargetInstrInfo.td36 def R16 : RegisterClass;
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td59 def R16 : LoongArchReg<16, "r16", ["t4"]>, DwarfRegNum<[16]>;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.td271 def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
287 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dadd.ll147 ; PRE4: addu $[[R16:[0-9]+]], $[[R2]], $[[R14]]
150 ; PRE4: addu $[[R19:[0-9]+]], $[[R16]], $[[R18]]
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVBaseInfo.h320 R16 = 14, enumerator
/llvm-project-15.0.7/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp127 ARC::R14, ARC::R15, ARC::R16, ARC::R17, ARC::R18, ARC::R19, ARC::R20,
/llvm-project-15.0.7/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp62 AVR::R14, AVR::R15, AVR::R16, AVR::R17, AVR::R18, AVR::R19, AVR::R20,
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp560 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in DecodeIntRegsRegisterClass()
575 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in DecodeGeneralSubRegsRegisterClass()

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