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/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dframe-chain-reserved-fp.ll1 …-none-eabi -filetype asm -o - %s -frame-pointer=all 2>&1 | FileCheck %s --check-prefix=RESERVED-R11
2 …o - %s -frame-pointer=all -mattr=+aapcs-frame-chain 2>&1 | FileCheck %s --check-prefix=RESERVED-R11
3 …s -frame-pointer=all -mattr=+aapcs-frame-chain-leaf 2>&1 | FileCheck %s --check-prefix=RESERVED-R11
5 …s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain 2>&1 | FileCheck %s --check-prefix=RESERVED-R11
6 …ame-pointer=non-leaf -mattr=+aapcs-frame-chain-leaf 2>&1 | FileCheck %s --check-prefix=RESERVED-R11
8 … - %s -frame-pointer=none -mattr=+aapcs-frame-chain 2>&1 | FileCheck %s --check-prefix=RESERVED-R11
9 … -frame-pointer=none -mattr=+aapcs-frame-chain-leaf 2>&1 | FileCheck %s --check-prefix=RESERVED-R11
15 ; RESERVED-R11-NOT: error: write to reserved register 'R7'
21 ; RESERVED-NONE-NOT: error: write to reserved register 'R11'
22 ; RESERVED-R11: error: write to reserved register 'R11'
H A Dinline-asm-clobber.ll10 ; CHECK: warning: inline asm clobber list contains reserved registers: R11
12 ; RWPI: warning: inline asm clobber list contains reserved registers: R11
13 ; NO_FP_ELIM: warning: inline asm clobber list contains reserved registers: R11, SP, PC
14 ; NO_FP_ELIM: warning: inline asm clobber list contains reserved registers: R11
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A Dframe-chain-reserved-fp.ll2 …o - %s -frame-pointer=all -mattr=+aapcs-frame-chain 2>&1 | FileCheck %s --check-prefix=RESERVED-R11
3 …s -frame-pointer=all -mattr=+aapcs-frame-chain-leaf 2>&1 | FileCheck %s --check-prefix=RESERVED-R11
5 …s -frame-pointer=non-leaf -mattr=+aapcs-frame-chain 2>&1 | FileCheck %s --check-prefix=RESERVED-R11
6 …ame-pointer=non-leaf -mattr=+aapcs-frame-chain-leaf 2>&1 | FileCheck %s --check-prefix=RESERVED-R11
8 … - %s -frame-pointer=none -mattr=+aapcs-frame-chain 2>&1 | FileCheck %s --check-prefix=RESERVED-R11
9 … -frame-pointer=none -mattr=+aapcs-frame-chain-leaf 2>&1 | FileCheck %s --check-prefix=RESERVED-R11
16 ; RESERVED-R11-NOT: error: write to reserved register 'R7'
22 ; RESERVED-NONE-NOT: error: write to reserved register 'R11'
23 ; RESERVED-R7-NOT: error: write to reserved register 'R11'
24 ; RESERVED-R11: error: write to reserved register 'R11'
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dfmul-v67.ll14 ; CHECK-DAG: [[R11:(r[0-9]+:[0-9]+)]] = dfmpyfix(r3:2,r1:0)
15 ; CHECK: [[R12:(r[0-9]+:[0-9]+)]] = dfmpyll([[R10]],[[R11]])
16 ; CHECK: [[R12]] += dfmpylh([[R10]],[[R11]])
17 ; CHECK: [[R12]] += dfmpylh([[R11]],[[R10]])
18 ; CHECK: [[R12]] += dfmpyhh([[R10]],[[R11]])
/llvm-project-15.0.7/compiler-rt/lib/builtins/hexagon/
H A Dfastmath_dlib_asm.S77 #define minmin R11:10 // exactly 0x800000000000000000LL
78 #define minminh R11
212 #define minmin R11:10 // exactly 0x800000000000000000LL
213 #define minminh R11
331 #define lmantc R11:10
332 #define mantch R11
H A Dfastmath2_dlib_asm.S70 #define minmin R11:10 // exactly 0x000000000000008001LL
171 #define minmin R11:10 // exactly 0x000000000000008001LL
269 #define lmantc R11:10
271 #define guard R11
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td36 def R11 : Ri<11, "r11">, DwarfRegNum<[11]>;
50 R11)>;
56 R11, CP, DP, SP, LR)> {
H A DXCoreCallingConv.td30 // The 'nest' parameter, if any, is passed in R11.
31 CCIfNest<CCAssignToReg<[R11]>>,
H A DXCoreInstrInfo.td638 let Uses = [R11], isCall=1 in
656 let Defs = [R11], isReMaterializable = 1 in
660 let Defs = [R11] in
685 let Defs = [R11], isReMaterializable = 1 in {
708 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
989 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
1003 let Uses=[R11] in {
1049 let Defs = [R11] in {
1052 [(set R11, (int_xcore_getid))]>;
1056 [(set R11, (int_xcore_geted))]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td36 def RR2 : LanaiReg<11, "rr2", [R11]>, DwarfRegAlias<R11>;
50 R10, RR1, R11, RR2, // programmer controlled registers
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallingConv.td122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
270 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
275 def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,
289 R11, R10, R9, R8,
294 LR, R11)>;
304 // When enforcing an AAPCS compliant frame chain, R11 is used as the frame
308 def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R11,
317 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
344 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
363 // FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and
[all …]
H A DARMBaseRegisterInfo.h54 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
66 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
94 case R11: case LR: in isSplitFPArea2Register()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86IndirectThunks.cpp97 BuildMI(&MF.front(), DebugLoc(), TII->get(X86::JMP64r)).addReg(X86::R11); in populateThunk()
98 MF.front().addLiveIn(X86::R11); in populateThunk()
161 ThunkReg = X86::R11; in populateThunk()
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/autohvx/
H A Dbswap.ll31 ; CHECK: [[R11:r[0-9]+]] = ##50529027
32 ; CHECK: [[V11:v[0-9]+]] = vsplat([[R11]])
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dcttz-v.ll33 ; MIPS64-DAG: and $[[R11:[0-9]+]], $[[R10]], $[[R9]]
34 ; MIPS64-DAG: clz $[[R12:[0-9]+]], $[[R11]]
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td47 def R11 : AVRReg<11, "r11">, DwarfRegNum<[11]>;
90 def R11R10 : AVRReg<10, "r11:r10", [R10, R11]>, DwarfRegNum<[10]>;
105 def R12R11 : AVRReg<11, "r12:r11", [R11, R12]>, DwarfRegNum<[11]>;
121 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
126 (add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6,
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp53 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
59 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
H A DMSP430RegisterInfo.td66 def R11 : MSP430RegWithSubregs<11, "r11", [R11B]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dtwo-extenders.s78 R11:10 = memd(##0x1000)
82 R11 = memb(##0x1000) define
H A Ddcfetch.s12 R13:12 = VALIGNB(R11:10,R9:8,P2)
/llvm-project-15.0.7/lldb/source/Plugins/Process/Windows/Common/x64/
H A DRegisterContextWindows_x64.cpp363 GPR_CASE(64, lldb_r11_x86_64, m_context.R11); in ReadRegister()
383 GPR_CASE(32, lldb_r11d_x86_64, static_cast<uint32_t>(m_context.R11)); in ReadRegister()
399 GPR_CASE(16, lldb_r11w_x86_64, static_cast<uint16_t>(m_context.R11)); in ReadRegister()
419 GPR_CASE(8, lldb_r11l_x86_64, static_cast<uint8_t>(m_context.R11)); in ReadRegister()
531 m_context.R11 = reg_value.GetAsUInt64(); in WriteRegister()
/llvm-project-15.0.7/llvm/test/tools/llvm-exegesis/X86/
H A Danalysis-clustering-algorithms.test201 - 'ROL64ri R11 R11 i_0x1'
218 - 'R11=0x0'
/llvm-project-15.0.7/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h69 case Lanai::R11: in getLanaiRegisterNumbering()
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp284 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) { in getMaskedTypeForICmpPair()
285 A = R11; in getMaskedTypeForICmpPair()
289 D = R11; in getMaskedTypeForICmpPair()
300 R11 = R1; in getMaskedTypeForICmpPair()
304 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) { in getMaskedTypeForICmpPair()
305 A = R11; in getMaskedTypeForICmpPair()
311 D = R11; in getMaskedTypeForICmpPair()
324 R11 = R2; in getMaskedTypeForICmpPair()
328 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) { in getMaskedTypeForICmpPair()
329 A = R11; in getMaskedTypeForICmpPair()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td49 R11, // Stack Ptr

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