| /llvm-project-15.0.7/llvm/utils/release/ |
| H A D | test-release.sh | 304 Phase="$1" 364 Phase="$1" 404 2>&1 | tee $LogDir/llvm.configure-Phase$Phase-$Flavor.log 413 2>&1 | tee $LogDir/llvm.configure-Phase$Phase-$Flavor.log 419 Phase="$1" 439 2>&1 | tee $LogDir/llvm.make-Phase$Phase-$Flavor.log > $redir 444 2>&1 | tee $LogDir/llvm.install-Phase$Phase-$Flavor.log > $redir 449 Phase="$1" 462 2>&1 | tee $LogDir/llvm.check-Phase$Phase-$Flavor.log ) ; then 463 deferred_error $Phase $Flavor "check-all failed" [all …]
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| /llvm-project-15.0.7/llvm/lib/Passes/ |
| H A D | PassBuilderPipelines.cpp | 240 static bool isLTOPreLink(ThinOrFullLTOPhase Phase) { in isLTOPreLink() argument 241 return Phase == ThinOrFullLTOPhase::ThinLTOPreLink || in isLTOPreLink() 242 Phase == ThinOrFullLTOPhase::FullLTOPreLink; in isLTOPreLink() 303 isLTOPreLink(Phase))); in buildO1FunctionSimplificationPipeline() 733 InlineContext{Phase, InlinePass::CGSCCInliner}, in buildInlinerPipeline() 781 buildFunctionSimplificationPipeline(Level, Phase), in buildInlinerPipeline() 840 Phase != ThinOrFullLTOPhase::ThinLTOPostLink) in buildModuleSimplificationPipeline() 907 if (Phase != ThinOrFullLTOPhase::ThinLTOPreLink && in buildModuleSimplificationPipeline() 908 Phase != ThinOrFullLTOPhase::FullLTOPreLink) in buildModuleSimplificationPipeline() 928 if (Phase == ThinOrFullLTOPhase::ThinLTOPostLink) in buildModuleSimplificationPipeline() [all …]
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| /llvm-project-15.0.7/llvm/unittests/Support/ |
| H A D | ThreadPool.cpp | 71 void waitForPhase(int Phase) { in waitForPhase() argument 74 LockGuard, [&] { return CurrentPhase == Phase || CurrentPhase < 0; }); in waitForPhase() 87 void setPhase(int Phase) { in setPhase() argument 90 assert(Phase == CurrentPhase + 1 || Phase < 0); in setPhase() 91 CurrentPhase = Phase; in setPhase()
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| /llvm-project-15.0.7/llvm/include/llvm/Passes/ |
| H A D | PassBuilder.h | 175 ThinOrFullLTOPhase Phase); 193 ThinOrFullLTOPhase Phase); 198 ThinOrFullLTOPhase Phase); 203 ThinOrFullLTOPhase Phase); 586 ThinOrFullLTOPhase Phase);
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| /llvm-project-15.0.7/clang-tools-extra/clangd/support/ |
| H A D | Trace.cpp | 79 void jsonEvent(llvm::StringRef Phase, llvm::json::Object &&Contents, in jsonEvent() argument 84 rawEvent(Phase, Contents); in jsonEvent() 156 void rawEvent(llvm::StringRef Phase, in rawEvent() argument 161 Out.attribute("ph", Phase); in rawEvent()
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| /llvm-project-15.0.7/bolt/include/bolt/Core/ |
| H A D | DynoStats.h | 162 StringRef Phase, const bool Flag, in callWithDynoStats() argument 173 outs() << "BOLT-INFO: program-wide dynostats after running " << Phase in callWithDynoStats()
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| /llvm-project-15.0.7/llvm/docs/ |
| H A D | LinkTimeOptimization.rst | 148 Phase 1 : Read LLVM Bitcode Files 166 Phase 2 : Symbol Resolution 175 Phase 3 : Optimize Bitcode Files 186 Phase 4 : Symbol Resolution after optimization
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| H A D | JITLink.rst | 424 #. Phase 1 503 This is the final step of Phase 1. 505 #. Phase 2 548 This is the final step of Phase 2. 550 #. Phase 3.
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| H A D | CodeGenerator.rst | 905 SelectionDAG LegalizeTypes Phase 934 SelectionDAG Legalize Phase 987 SelectionDAG Optimization Phase: the DAG Combiner 1014 SelectionDAG Select Phase 1167 SelectionDAG Scheduling and Formation Phase 1438 the *SSA Deconstruction Phase*. The SSA form simplifies many analyses that are
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| H A D | WritingAnLLVMBackend.rst | 782 during the SelectionDAG Select Phase described in :doc:`CodeGenerator`. 1340 The SelectionDAG Legalize Phase
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| /llvm-project-15.0.7/clang/lib/Driver/ |
| H A D | Driver.cpp | 4084 for (phases::ID Phase : PL) { in BuildActions() local 4089 Current, InputArg, Phase, PL.back(), FullPL); in BuildActions() 4094 if (Phase == phases::Link) { in BuildActions() 4108 if (Phase == phases::IfsMerge) { in BuildActions() 4230 for (auto Phase : PhaseList) { in BuildActions() local 4231 switch (Phase) { in BuildActions() 4246 assert(Phase == PhaseList.back() && in BuildActions() 4454 for (phases::ID Phase : PL) { in BuildOffloadingActions() local 4455 if (Phase == phases::Link) { in BuildOffloadingActions() 4462 A = ConstructPhaseAction(C, Args, Phase, A, Kind); in BuildOffloadingActions() [all …]
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| /llvm-project-15.0.7/llvm/docs/Proposals/ |
| H A D | VectorPredication.rst | 74 - Phase out VP intrinsics, only keeping those that are not equivalent to
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| /llvm-project-15.0.7/llvm/include/llvm/Transforms/IPO/ |
| H A D | Attributor.h | 1393 if (ForceUpdate && Phase == AttributorPhase::UPDATE) 1403 if (Phase == AttributorPhase::SEEDING && !shouldSeedAttribute(AA)) { 1449 if (Phase == AttributorPhase::MANIFEST) { 1457 AttributorPhase OldPhase = Phase; 1458 Phase = AttributorPhase::UPDATE; 1462 Phase = OldPhase; 1543 if (Phase == AttributorPhase::SEEDING || Phase == AttributorPhase::UPDATE) 2206 } Phase = AttributorPhase::SEEDING;
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| /llvm-project-15.0.7/libcxxabi/src/ |
| H A D | aix_state_tab_eh.inc | 306 // Do Phase 1 308 // None of these flags should be set during Phase 1. 551 // Phase 1 search: All we're looking for in phase 1 is a handler that 556 // Phase 2 cleanup:
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| /llvm-project-15.0.7/clang/include/clang/Driver/ |
| H A D | Driver.h | 586 Compilation &C, const llvm::opt::ArgList &Args, phases::ID Phase,
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| /llvm-project-15.0.7/llvm/docs/HistoricalNotes/ |
| H A D | 2003-06-25-Reoptimizer1.txt | 68 Phase behavior
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | O3-pipeline.ll | 204 ; CHECK-NEXT: Falkor HW Prefetch Fix Late Phase
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| /llvm-project-15.0.7/llvm/lib/Transforms/IPO/ |
| H A D | Attributor.cpp | 2232 Phase = AttributorPhase::UPDATE; in run() 2245 Phase = AttributorPhase::MANIFEST; in run() 2248 Phase = AttributorPhase::CLEANUP; in run() 2261 assert(Phase == AttributorPhase::UPDATE && in updateAA()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1813 for (int Phase = 0; Phase < 2; ++Phase) { in ExpandBVWithShuffles() local 1822 if (Phase) in ExpandBVWithShuffles() 1851 if (Phase) in ExpandBVWithShuffles() 1875 else if (Phase) in ExpandBVWithShuffles() 1884 if (Phase) in ExpandBVWithShuffles()
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| /llvm-project-15.0.7/llvm/docs/TableGen/ |
| H A D | BackGuide.rst | 828 TableGen Phase Timing 847 TableGen Phase Timing
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| /llvm-project-15.0.7/mlir/docs/ |
| H A D | BufferDeallocationInternals.md | 598 # Post Phase
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| /llvm-project-15.0.7/clang/docs/ |
| H A D | InternalsManual.rst | 1152 This is somewhat similar to how the parser handles Translation Phase 6 of C99:
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