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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-intrinsics-gather-prefetches-scalar-base-vector-indexes.ll4 ; PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>] -> 32-bit indexes
23 ; PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod>] -> 32-bit unpacked indexes
42 ; PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.D] -> 64-bit indexes
54 ; PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>] -> 32-bit indexes
73 ; PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #1] -> 32-bit unpacked indexes
92 ; PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.D] -> 64-bit indexes
104 ; PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>] -> 32-bit indexes
123 ; PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #2] -> 32-bit unpacked indexes
142 ; PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.D] -> 64-bit indexes
154 ; PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>] -> 32-bit indexes
[all …]
H A Dsve-intrinsics-gather-prefetches-vect-base-imm-offset.ll4 ; PRFB <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element
5 …_sve_prfb_gather_scalar_offset_nx4vi32(<vscale x 4 x i32> %bases, <vscale x 4 x i1> %Pg) nounwind {
10 …call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x…
14 ; PRFB <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element
15 …_sve_prfb_gather_scalar_offset_nx2vi64(<vscale x 2 x i64> %bases, <vscale x 2 x i1> %Pg) nounwind {
24 ; PRFH <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element
34 ; PRFH <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element
44 ; PRFW <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element
54 ; PRFW <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element
64 ; PRFD <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element
[all …]
H A Dsve-intrinsics-gather-prefetches-vect-base-invalid-imm-offset.ll4 ; PRFB <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element, imm = 0, 1, ..., 31
10 …call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x…
20 …call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x…
30 …call void @llvm.aarch64.sve.prfb.gather.scalar.offset.nx4vi32(<vscale x 4 x i1> %Pg, <vscale x 4 x…
34 ; PRFB <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element, imm = 0, 1, ..., 31
66 ; PRFH <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element, imm = 0, 2, ..., 62
106 ; PRFH <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element, imm = 0, 2, ..., 62
148 ; PRFW <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element, imm = 0, 4, ..., 124
188 ; PRFW <prfop>, <Pg>, [<Zn>.D{, #<imm>}] -> 64-bit element, imm = 0, 4, ..., 124
230 ; PRFD <prfop>, <Pg>, [<Zn>.S{, #<imm>}] -> 32-bit element, imm = 0, 8, ..., 248
[all …]
H A Dsve-pred-log.ll3 define <vscale x 16 x i1> @vselect_16(<vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 …
7 %res = select <vscale x 16 x i1> %Pg, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd
11 define <vscale x 8 x i1> @vselect_8(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1>…
15 %res = select <vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd
19 define <vscale x 4 x i1> @vselect_4(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1>…
23 %res = select <vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd
31 %res = select <vscale x 2 x i1> %Pg, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd
39 %res = select <vscale x 1 x i1> %Pg, <vscale x 1 x i1> %Pn, <vscale x 1 x i1> %Pd
51 define <vscale x 8 x i1> @and_8(<vscale x 8 x i1> %Pg, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd…
59 define <vscale x 4 x i1> @and_4(<vscale x 4 x i1> %Pg, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd…
[all …]
H A Dsve-intrinsics-ldN-reg+reg-addr-mode.ll6 define <vscale x 32 x i8> @ld2.nxv32i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) {
17 define <vscale x 16 x i16> @ld2.nxv16i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a) {
27 define <vscale x 16 x half> @ld2.nxv16f16(<vscale x 8 x i1> %Pg, half *%addr, i64 %a) {
48 define <vscale x 8 x i32> @ld2.nxv8i32(<vscale x 4 x i1> %Pg, i32 *%addr, i64 %a) {
58 define <vscale x 8 x float> @ld2.nxv8f32(<vscale x 4 x i1> %Pg, float *%addr, i64 %a) {
69 define <vscale x 4 x i64> @ld2.nxv4i64(<vscale x 2 x i1> %Pg, i64 *%addr, i64 %a) {
90 define <vscale x 48 x i8> @ld3.nxv48i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) {
101 define <vscale x 24 x i16> @ld3.nxv24i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a) {
153 define <vscale x 6 x i64> @ld3.nxv6i64(<vscale x 2 x i1> %Pg, i64 *%addr, i64 %a) {
174 define <vscale x 64 x i8> @ld4.nxv64i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) {
[all …]
H A Dsve-intrinsics-ldN-reg+imm-addr-mode.ll12 define <vscale x 32 x i8> @ld2.nxv32i8(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
82 define <vscale x 16 x i16> @ld2.nxv16i16(<vscale x 8 x i1> %Pg, <vscale x 8 x i16>* %addr) {
93 define <vscale x 16 x half> @ld2.nxv16f16(<vscale x 8 x i1> %Pg, <vscale x 8 x half>* %addr) {
116 define <vscale x 8 x i32> @ld2.nxv8i32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32>* %addr) {
139 define <vscale x 4 x i64> @ld2.nxv4i64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64>* %addr) {
162 define <vscale x 48 x i8> @ld3.nxv48i8(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
244 define <vscale x 24 x i16> @ld3.nxv24i16(<vscale x 8 x i1> %Pg, <vscale x 8 x i16> *%addr) {
278 define <vscale x 12 x i32> @ld3.nxv12i32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> *%addr) {
301 define <vscale x 6 x i64> @ld3.nxv6i64(<vscale x 2 x i1> %Pg, <vscale x 2 x i64> *%addr) {
324 define <vscale x 64 x i8> @ld4.nxv64i8(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> *%addr) {
[all …]
H A Dsve-intrinsics-ldN-sret-reg+imm-addr-mode.ll12 define { <vscale x 16 x i8>, <vscale x 16 x i8> } @ld2.nxv32i8(<vscale x 16 x i1> %Pg, <vscale x 16…
24 define { <vscale x 16 x i8>, <vscale x 16 x i8> } @ld2.nxv32i8_lower_bound(<vscale x 16 x i1> %Pg, …
36 define { <vscale x 16 x i8>, <vscale x 16 x i8> } @ld2.nxv32i8_upper_bound(<vscale x 16 x i1> %Pg, …
48 …>, <vscale x 16 x i8> } @ld2.nxv32i8_not_multiple_of_2(<vscale x 16 x i1> %Pg, <vscale x 16 x i8> …
85 define { <vscale x 8 x i16>, <vscale x 8 x i16> } @ld2.nxv16i16(<vscale x 8 x i1> %Pg, <vscale x 8 …
97 define { <vscale x 8 x half>, <vscale x 8 x half> } @ld2.nxv16f16(<vscale x 8 x i1> %Pg, <vscale x …
109 define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @ld2.nxv16bf16(<vscale x 8 x i1> %Pg, <vsca…
122 define { <vscale x 4 x i32>, <vscale x 4 x i32> } @ld2.nxv8i32(<vscale x 4 x i1> %Pg, <vscale x 4 x…
134 define { <vscale x 4 x float>, <vscale x 4 x float> } @ld2.nxv8f32(<vscale x 4 x i1> %Pg, <vscale x…
147 define { <vscale x 2 x i64>, <vscale x 2 x i64> } @ld2.nxv4i64(<vscale x 2 x i1> %Pg, <vscale x 2 x…
[all …]
H A Dsve-intrinsics-ldN-sret-reg+reg-addr-mode.ll6 define { <vscale x 16 x i8>, <vscale x 16 x i8> } @ld2.nxv32i8(<vscale x 16 x i1> %Pg, i8 *%addr, i…
17 define { <vscale x 8 x i16>, <vscale x 8 x i16> } @ld2.nxv16i16(<vscale x 8 x i1> %Pg, i16 *%addr, …
27 define { <vscale x 8 x half>, <vscale x 8 x half> } @ld2.nxv16f16(<vscale x 8 x i1> %Pg, half *%add…
37 define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @ld2.nxv16bf16(<vscale x 8 x i1> %Pg, bfloa…
48 define { <vscale x 4 x i32>, <vscale x 4 x i32> } @ld2.nxv8i32(<vscale x 4 x i1> %Pg, i32 *%addr, i…
58 define { <vscale x 4 x float>, <vscale x 4 x float> } @ld2.nxv8f32(<vscale x 4 x i1> %Pg, float *%a…
69 define { <vscale x 2 x i64>, <vscale x 2 x i64> } @ld2.nxv4i64(<vscale x 2 x i1> %Pg, i64 *%addr, i…
79 define { <vscale x 2 x double>, <vscale x 2 x double> } @ld2.nxv4f64(<vscale x 2 x i1> %Pg, double …
90 … <vscale x 16 x i8>, <vscale x 16 x i8> } @ld3.nxv48i8(<vscale x 16 x i1> %Pg, i8 *%addr, i64 %a) {
101 … <vscale x 8 x i16>, <vscale x 8 x i16> } @ld3.nxv24i16(<vscale x 8 x i1> %Pg, i16 *%addr, i64 %a)…
[all …]
H A Daarch64-sve-asm.ll56 define <vscale x 8 x half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscal…
57 …alf> asm "fadd $0.h, $1/m, $2.h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half>…
67 define <vscale x 4 x i32> @test_incp(<vscale x 16 x i1> %Pg, <vscale x 4 x i32> %Zn) {
68 …%1 = tail call <vscale x 4 x i32> asm "incp $0.s, $1", "=w,@3Upa,0"(<vscale x 16 x i1> %Pg, <vscal…
H A Dsve-ptest-removal-whilerw.mir167 ; PTEST is not redundant when it's Pg operand is not an all active predicate
207 ; PTEST is not redundant when it's Pg operand is not an all active predicate
247 ; PTEST is not redundant when it's Pg operand is not an all active predicate
287 ; PTEST is not redundant when it's Pg operand is not an all active predicate
H A Dsve-ptest-removal-whilewr.mir167 ; PTEST is not redundant when it's Pg operand is not an all active predicate
207 ; PTEST is not redundant when it's Pg operand is not an all active predicate
247 ; PTEST is not redundant when it's Pg operand is not an all active predicate
287 ; PTEST is not redundant when it's Pg operand is not an all active predicate
H A Dsve-ptest-removal-whilehi.mir305 ; PTEST is not redundant when it's Pg operand is not an all active predicate
345 ; PTEST is not redundant when it's Pg operand is not an all active predicate
385 ; PTEST is not redundant when it's Pg operand is not an all active predicate
425 ; PTEST is not redundant when it's Pg operand is not an all active predicate
H A Dsve-ptest-removal-whilehs.mir305 ; PTEST is not redundant when it's Pg operand is not an all active predicate
345 ; PTEST is not redundant when it's Pg operand is not an all active predicate
385 ; PTEST is not redundant when it's Pg operand is not an all active predicate
425 ; PTEST is not redundant when it's Pg operand is not an all active predicate
H A Dsve-ptest-removal-whilele.mir305 ; PTEST is not redundant when it's Pg operand is not an all active predicate
345 ; PTEST is not redundant when it's Pg operand is not an all active predicate
385 ; PTEST is not redundant when it's Pg operand is not an all active predicate
425 ; PTEST is not redundant when it's Pg operand is not an all active predicate
H A Dsve-ptest-removal-whilels.mir305 ; PTEST is not redundant when it's Pg operand is not an all active predicate
345 ; PTEST is not redundant when it's Pg operand is not an all active predicate
385 ; PTEST is not redundant when it's Pg operand is not an all active predicate
425 ; PTEST is not redundant when it's Pg operand is not an all active predicate
H A Dsve-ptest-removal-whilege.mir305 ; PTEST is not redundant when it's Pg operand is not an all active predicate
345 ; PTEST is not redundant when it's Pg operand is not an all active predicate
385 ; PTEST is not redundant when it's Pg operand is not an all active predicate
425 ; PTEST is not redundant when it's Pg operand is not an all active predicate
H A Dsve-ptest-removal-whilelo.mir305 ; PTEST is not redundant when it's Pg operand is not an all active predicate
345 ; PTEST is not redundant when it's Pg operand is not an all active predicate
385 ; PTEST is not redundant when it's Pg operand is not an all active predicate
425 ; PTEST is not redundant when it's Pg operand is not an all active predicate
H A Dsve-ptest-removal-whilelt.mir305 ; PTEST is not redundant when it's Pg operand is not an all active predicate
345 ; PTEST is not redundant when it's Pg operand is not an all active predicate
385 ; PTEST is not redundant when it's Pg operand is not an all active predicate
425 ; PTEST is not redundant when it's Pg operand is not an all active predicate
H A Dsve-ptest-removal-whilegt.mir305 ; PTEST is not redundant when it's Pg operand is not an all active predicate
345 ; PTEST is not redundant when it's Pg operand is not an all active predicate
385 ; PTEST is not redundant when it's Pg operand is not an all active predicate
425 ; PTEST is not redundant when it's Pg operand is not an all active predicate
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedA64FX.td2301 // [ 1] "abs $Zd, $Pg/m, $Zn";
2337 // [13] "andv $Vd, $Pg, $Zn";
2370 // [24] "brka $Pd, $Pg/m, $Pn";
2373 // [25] "brka $Pd, $Pg/z, $Pn";
2379 // [27] "brkb $Pd, $Pg/m, $Pn";
2382 // [28] "brkb $Pd, $Pg/z, $Pn";
2505 // [69] "cntp $Rd, $Pg, $Pn";
2547 // [83] "decp $Rdn, $Pg";
2550 // [84] "decp $Zdn, $Pg";
2586 // [96] "eorv $Vd, $Pg, $Zn";
[all …]
H A DSVEInstrFormats.td519 : Pat<(vt (op pt:$Pg, (vselect pt:$Pg, vt:$Zs1, (SVEDup0)),
658 bits<4> Pg;
681 bits<4> Pg;
727 bits<4> Pg;
873 bits<4> Pg;
1599 bits<4> Pg;
1654 bits<4> Pg;
1853 bits<3> Pg;
1892 bits<3> Pg;
2071 bits<3> Pg;
[all …]
H A DSMEInstrFormats.td273 bits<3> Pg;
282 let Inst{12-10} = Pg;
450 bits<3> Pg;
459 let Inst{12-10} = Pg;
655 bits<3> Pg;
663 let Inst{12-10} = Pg;
844 bits<3> Pg;
852 let Inst{12-10} = Pg;
1057 asm, "\t$Zd, $Pg/m, $Zn", "", []>,
1060 bits<3> Pg;
[all …]
H A DAArch64SVEInstrInfo.td478 (CNOT_ZPmZ_B $Op2, $Pg, $Op2)>;
480 (CNOT_ZPmZ_H $Op2, $Pg, $Op2)>;
482 (CNOT_ZPmZ_S $Op2, $Pg, $Op2)>;
484 (CNOT_ZPmZ_D $Op2, $Pg, $Op2)>;
2090 def : InstAlias<"mov $Pd, $Pg/m, $Pn",
2094 def : InstAlias<"mov $Pd, $Pg/z, $Pn",
2099 def : InstAlias<"movs $Pd, $Pg/z, $Pn",
2102 def : InstAlias<"not $Pd, $Pg/z, $Pn",
2103 (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg), 1>;
2105 def : InstAlias<"nots $Pd, $Pg/z, $Pn",
[all …]
H A DAArch64TargetTransformInfo.cpp658 if (!Pg) in instCombineSVEDup()
661 if (Pg->getIntrinsicID() != Intrinsic::aarch64_sve_ptrue) in instCombineSVEDup()
665 cast<ConstantInt>(Pg->getOperand(0))->getZExtValue(); in instCombineSVEDup()
698 auto *Pg = dyn_cast<IntrinsicInst>(II.getArgOperand(0)); in instCombineSVECmpNE() local
699 if (!Pg || Pg->getIntrinsicID() != Intrinsic::aarch64_sve_ptrue) in instCombineSVECmpNE()
703 cast<ConstantInt>(Pg->getOperand(0))->getZExtValue(); in instCombineSVECmpNE()
796 Value *Pg = II.getArgOperand(0); in instCombineSVELast() local
822 auto *C = dyn_cast<Constant>(Pg); in instCombineSVELast()
832 auto *IntrPG = dyn_cast<IntrinsicInst>(Pg); in instCombineSVELast()
856 auto *PgVTy = cast<ScalableVectorType>(Pg->getType()); in instCombineSVELast()
[all …]
H A DAArch64ISelLowering.cpp16324 Pg = DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, MVT::nxv16i1, Pg); in getPTest()
16326 Pg = getSVEPredicateBitCast(MVT::nxv16i1, Pg, DAG); in getPTest()
16454 SDValue Pg = N->getOperand(1); in convertMergedOpToPredOp() local
16459 if (isAllActivePredicate(DAG, Pg)) { in convertMergedOpToPredOp()
17344 SDValue Pg = N->getOperand(1); in performGLD1Combine() local
21027 return Pg; in convertFixedMaskToScalableVector()
21317 SmallVector<SDValue, 4> Operands = {Pg}; in LowerToPredicatedOp()
21345 SmallVector<SDValue, 4> Operands = {Pg}; in LowerToPredicatedOp()
21413 Pg, AccOp, VecOp); in LowerVECREDUCE_SEQ_FADD()
21449 Pg = DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, MVT::nxv2i1, Pg); in LowerPredReductionToSVE()
[all …]

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