Lines Matching refs:Pg
11797 SDValue Pg = getPredicateForScalableVector(DAG, dl, VT); in LowerDIV() local
11799 DAG.getNode(AArch64ISD::SRAD_MERGE_OP1, dl, VT, Pg, Op->getOperand(0), in LowerDIV()
15018 static SDValue getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op,
15064 SDValue Pg = getPTrue(DAG, SDLoc(N), VT, AArch64SVEPredPattern::all); in performFirstTrueTestVectorCombine() local
15065 return getPTest(DAG, N->getValueType(0), Pg, N0, AArch64CC::FIRST_ACTIVE); in performFirstTrueTestVectorCombine()
15101 SDValue Pg = getPTrue(DAG, SDLoc(N), OpVT, AArch64SVEPredPattern::all); in performLastTrueTestVectorCombine() local
15102 return getPTest(DAG, N->getValueType(0), Pg, N0, AArch64CC::LAST_ACTIVE); in performLastTrueTestVectorCombine()
16304 static SDValue getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op, in getPTest() argument
16312 assert(Op.getValueType() == Pg.getValueType() && in getPTest()
16324 Pg = DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, MVT::nxv16i1, Pg); in getPTest()
16326 Pg = getSVEPredicateBitCast(MVT::nxv16i1, Pg, DAG); in getPTest()
16331 SDValue Test = DAG.getNode(AArch64ISD::PTEST, DL, MVT::Other, Pg, Op); in getPTest()
16454 SDValue Pg = N->getOperand(1); in convertMergedOpToPredOp() local
16459 if (isAllActivePredicate(DAG, Pg)) { in convertMergedOpToPredOp()
16463 return DAG.getNode(Opc, SDLoc(N), N->getValueType(0), Pg, Op1, Op2); in convertMergedOpToPredOp()
17344 SDValue Pg = N->getOperand(1); in performGLD1Combine() local
17366 if (ExtPg == Pg && ExtFromEVT == MVT::i32) { in performGLD1Combine()
17374 {Chain, Pg, Base, UnextendedOffset, Ty}); in performGLD1Combine()
20991 auto Pg = getPredicateForFixedLengthVector(DAG, DL, VT); in LowerFixedLengthVectorLoadToSVE() local
20999 LoadVT, DL, Load->getChain(), Load->getBasePtr(), Load->getOffset(), Pg, in LowerFixedLengthVectorLoadToSVE()
21010 Pg, Result, DAG.getUNDEF(ContainerVT)); in LowerFixedLengthVectorLoadToSVE()
21024 auto Pg = getPredicateForFixedLengthVector(DAG, DL, InVT); in convertFixedMaskToScalableVector() local
21027 return Pg; in convertFixedMaskToScalableVector()
21032 return DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, DL, Pg.getValueType(), in convertFixedMaskToScalableVector()
21033 {Pg, Op1, Op2, DAG.getCondCode(ISD::SETNE)}); in convertFixedMaskToScalableVector()
21089 auto Pg = getPredicateForFixedLengthVector(DAG, DL, VT); in LowerFixedLengthVectorStoreToSVE() local
21096 NewValue = DAG.getNode(AArch64ISD::FP_ROUND_MERGE_PASSTHRU, DL, TruncVT, Pg, in LowerFixedLengthVectorStoreToSVE()
21104 Store->getBasePtr(), Store->getOffset(), Pg, MemVT, in LowerFixedLengthVectorStoreToSVE()
21142 SDValue Pg = getPredicateForFixedLengthVector(DAG, dl, VT); in LowerFixedLengthVectorIntDivideToSVE() local
21143 SDValue Res = DAG.getNode(AArch64ISD::SRAD_MERGE_OP1, dl, ContainerVT, Pg, Op1, Op2); in LowerFixedLengthVectorIntDivideToSVE()
21310 auto Pg = getPredicateForVector(DAG, DL, VT); in LowerToPredicatedOp() local
21317 SmallVector<SDValue, 4> Operands = {Pg}; in LowerToPredicatedOp()
21345 SmallVector<SDValue, 4> Operands = {Pg}; in LowerToPredicatedOp()
21404 SDValue Pg = getPredicateForVector(DAG, DL, SrcVT); in LowerVECREDUCE_SEQ_FADD() local
21413 Pg, AccOp, VecOp); in LowerVECREDUCE_SEQ_FADD()
21428 SDValue Pg = getPredicateForVector(DAG, DL, OpVT); in LowerPredReductionToSVE() local
21434 if (isAllActivePredicate(DAG, Pg) && OpVT == MVT::nxv16i1) in LowerPredReductionToSVE()
21439 return getPTest(DAG, VT, Pg, Op, AArch64CC::ANY_ACTIVE); in LowerPredReductionToSVE()
21441 Op = DAG.getNode(ISD::XOR, DL, OpVT, Op, Pg); in LowerPredReductionToSVE()
21442 return getPTest(DAG, VT, Pg, Op, AArch64CC::NONE_ACTIVE); in LowerPredReductionToSVE()
21449 Pg = DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, MVT::nxv2i1, Pg); in LowerPredReductionToSVE()
21453 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i64, ID, Pg, Op); in LowerPredReductionToSVE()
21482 SDValue Pg = getPredicateForVector(DAG, DL, SrcVT); in LowerReductionToSVE() local
21483 SDValue Rdx = DAG.getNode(Opcode, DL, RdxVT, Pg, VecOp); in LowerReductionToSVE()
21532 auto Pg = getPredicateForFixedLengthVector(DAG, DL, InVT); in LowerFixedLengthVectorSetccToSVE() local
21534 EVT CmpVT = Pg.getValueType(); in LowerFixedLengthVectorSetccToSVE()
21536 {Pg, Op1, Op2, Op.getOperand(2)}); in LowerFixedLengthVectorSetccToSVE()
21583 SDValue Pg = getPredicateForFixedLengthVector(DAG, DL, SrcVT); in LowerFixedLengthConcatVectorsToSVE() local
21587 Op = DAG.getNode(AArch64ISD::SPLICE, DL, ContainerVT, Pg, SrcOp1, SrcOp2); in LowerFixedLengthConcatVectorsToSVE()
21600 SDValue Pg = getPredicateForVector(DAG, DL, VT); in LowerFixedLengthFPExtendToSVE() local
21612 Pg, Val, DAG.getUNDEF(ContainerVT)); in LowerFixedLengthFPExtendToSVE()
21629 SDValue Pg = getPredicateForVector(DAG, DL, RoundVT); in LowerFixedLengthFPRoundToSVE() local
21632 Val = DAG.getNode(AArch64ISD::FP_ROUND_MERGE_PASSTHRU, DL, RoundVT, Pg, Val, in LowerFixedLengthFPRoundToSVE()
21659 SDValue Pg = getPredicateForVector(DAG, DL, VT); in LowerFixedLengthIntToFPToSVE() local
21668 Val = DAG.getNode(Opcode, DL, ContainerDstVT, Pg, Val, in LowerFixedLengthIntToFPToSVE()
21674 SDValue Pg = getPredicateForVector(DAG, DL, CvtVT); in LowerFixedLengthIntToFPToSVE() local
21677 Val = DAG.getNode(Opcode, DL, CvtVT, Pg, Val, DAG.getUNDEF(CvtVT)); in LowerFixedLengthIntToFPToSVE()
21706 SDValue Pg = getPredicateForVector(DAG, DL, VT); in LowerFixedLengthFPToIntToSVE() local
21713 Val = DAG.getNode(Opcode, DL, ContainerDstVT, Pg, Val, in LowerFixedLengthFPToIntToSVE()
21718 SDValue Pg = getPredicateForVector(DAG, DL, CvtVT); in LowerFixedLengthFPToIntToSVE() local
21723 Val = DAG.getNode(Opcode, DL, CvtVT, Pg, Val, DAG.getUNDEF(CvtVT)); in LowerFixedLengthFPToIntToSVE()