| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 227 } else if (PartVT.isFloatingPoint()) { in getCopyFromParts()
486 unsigned PartBits = PartVT.getSizeInBits(); in getCopyToParts()
495 EVT PartEVT = PartVT; in getCopyToParts()
514 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && in getCopyToParts()
519 if (PartVT == MVT::x86mmx) in getCopyToParts()
528 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && in getCopyToParts()
533 if (PartVT == MVT::x86mmx) in getCopyToParts()
608 if (!PartVT.isVector()) in widenVectorToPartType()
626 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT), in widenVectorToPartType()
653 EVT PartEVT = PartVT; in getCopyToPartsVector()
[all …]
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| H A D | LegalizeVectorTypes.cpp | 4774 EVT PartVT = EVT::getVectorVT(*DAG.getContext(), EltVT, in WidenVecRes_EXTRACT_SUBVECTOR() local
4777 if (getTypeAction(PartVT) != TargetLowering::TypeWidenVector) { in WidenVecRes_EXTRACT_SUBVECTOR()
4782 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, PartVT, InOp, in WidenVecRes_EXTRACT_SUBVECTOR()
4785 Parts.push_back(DAG.getUNDEF(PartVT)); in WidenVecRes_EXTRACT_SUBVECTOR()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1564 EVT PartVT = VT; in getVectorTypeBreakdown() local
1567 LK = getTypeConversion(Context, PartVT); in getVectorTypeBreakdown()
1568 PartVT = LK.second; in getVectorTypeBreakdown()
1571 if (!PartVT.isVector()) { in getVectorTypeBreakdown()
1578 PartVT.getVectorElementCount().getKnownMinValue()); in getVectorTypeBreakdown()
1579 IntermediateVT = PartVT; in getVectorTypeBreakdown()
1683 MVT PartVT = in GetReturnInfo() local
1698 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0)); in GetReturnInfo()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 557 unsigned NumParts, MVT PartVT,
563 MVT PartVT, EVT ValueVT,
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| H A D | RISCVISelLowering.cpp | 11287 EVT PartVT = PartValue.getValueType(); in LowerCall() local
11288 if (PartVT.isScalableVector()) in LowerCall()
11290 StoredSize += PartVT.getStoreSize(); in LowerCall()
12394 if (IsABIRegCopy && ValueVT == MVT::f16 && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
12406 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in splitValueIntoRegisterParts()
12409 EVT PartEltVT = PartVT.getVectorElementType(); in splitValueIntoRegisterParts()
12430 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in splitValueIntoRegisterParts()
12433 DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT), in splitValueIntoRegisterParts()
12445 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
12457 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in joinRegisterPartsIntoValue()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 561 unsigned NumParts, MVT PartVT,
566 MVT PartVT, EVT ValueVT,
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| H A D | SystemZISelLowering.cpp | 1453 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
1456 ((NumParts == 1 && PartVT == MVT::Untyped) || in splitValueIntoRegisterParts()
1457 (NumParts == 2 && PartVT == MVT::i64))) && in splitValueIntoRegisterParts()
1469 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
1471 ((NumParts == 1 && PartVT == MVT::Untyped) || in joinRegisterPartsIntoValue()
1472 (NumParts == 2 && PartVT == MVT::i64))) && in joinRegisterPartsIntoValue()
1729 MVT PartVT = getRegisterTypeForCallingConv(Ctx, CLI.CallConv, OrigArgVT); in LowerCall() local
1731 SlotVT = EVT::getIntegerVT(Ctx, PartVT.getSizeInBits() * N); in LowerCall()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 890 SDValue *Parts, unsigned NumParts, MVT PartVT,
896 MVT PartVT, EVT ValueVT,
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| H A D | ARMISelLowering.cpp | 4397 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
4401 PartVT == MVT::f32) { in splitValueIntoRegisterParts()
4403 unsigned PartBits = PartVT.getSizeInBits(); in splitValueIntoRegisterParts()
4406 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in splitValueIntoRegisterParts()
4415 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
4418 PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
4420 unsigned PartBits = PartVT.getSizeInBits(); in joinRegisterPartsIntoValue()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1627 SDValue *Parts, unsigned NumParts, MVT PartVT,
1633 MVT PartVT, EVT ValueVT,
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| H A D | X86ISelLowering.cpp | 2748 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
2751 if (IsABIRegCopy && ValueVT == MVT::bf16 && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
2753 unsigned PartBits = PartVT.getSizeInBits(); in splitValueIntoRegisterParts()
2756 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in splitValueIntoRegisterParts()
2765 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
2767 if (IsABIRegCopy && ValueVT == MVT::bf16 && PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
2769 unsigned PartBits = PartVT.getSizeInBits(); in joinRegisterPartsIntoValue()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 1157 SDValue *Parts, unsigned NumParts, MVT PartVT,
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| H A D | PPCISelLowering.cpp | 17811 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
17817 if (PartVT == MVT::f64 && in splitValueIntoRegisterParts()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 3991 unsigned NumParts, MVT PartVT, in splitValueIntoRegisterParts() argument
4000 MVT PartVT, EVT ValueVT, in joinRegisterPartsIntoValue() argument
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 623 MVT PartVT = MVT::getVectorVT(VecTy.getVectorElementType(), OpsPerWord); in buildHvxVectorReg() local
625 SDValue W = buildVector32(Values.slice(i, OpsPerWord), dl, PartVT, DAG); in buildHvxVectorReg()
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