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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dload-store-left-right.ll35 ; MIPS32R6: lw $2, 0($[[PTR]])
50 ; MIPS64R6: lw $2, 0($[[PTR]])
67 ; MIPS32R6: sw $4, 0($[[PTR]])
82 ; MIPS64R6: sw $4, 0($[[PTR]])
103 ; MIPS32R6-DAG: lw $2, 0($[[PTR]])
104 ; MIPS32R6-DAG: lw $3, 4($[[PTR]])
119 ; MIPS64R6: ld $2, 0($[[PTR]])
136 ; MIPS32R6-EL: lw $2, 0($[[PTR]])
138 ; MIPS32R6-EB: lw $3, 0($[[PTR]])
154 ; MIPS64R6: lw $2, 0($[[PTR]])
[all …]
/llvm-project-15.0.7/openmp/runtime/src/
H A Dz_Windows_NT-586_asm.asm93 mov DWORD PTR _eax$[ edi ], eax
94 mov DWORD PTR _ebx$[ edi ], ebx
95 mov DWORD PTR _ecx$[ edi ], ecx
96 mov DWORD PTR _edx$[ edi ], edx
230 lock cmpxchg8b QWORD PTR [edi]
326 fld DWORD PTR [esi]
466 fldcw WORD PTR [eax]
653 mov DWORD PTR 4[ r10 ], ebx
654 mov DWORD PTR 8[ r10 ], ecx
1133 fldcw WORD PTR [rcx]
[all …]
/llvm-project-15.0.7/clang/include/clang/AST/
H A DEvaluatedExprVisitor.h38 #define PTR(CLASS) typename Ptr<CLASS>::type macro
44 void VisitDeclRefExpr(PTR(DeclRefExpr) E) { } in VisitDeclRefExpr()
45 void VisitOffsetOfExpr(PTR(OffsetOfExpr) E) { } in VisitOffsetOfExpr()
48 void VisitBlockExpr(PTR(BlockExpr) E) { } in VisitBlockExpr()
52 void VisitMemberExpr(PTR(MemberExpr) E) { in VisitMemberExpr()
57 void VisitChooseExpr(PTR(ChooseExpr) E) { in VisitChooseExpr()
87 void VisitCallExpr(PTR(CallExpr) CE) { in VisitCallExpr()
92 void VisitLambdaExpr(PTR(LambdaExpr) LE) { in VisitLambdaExpr()
103 void VisitStmt(PTR(Stmt) S) { in VisitStmt()
109 void VisitIfStmt(PTR(IfStmt) If) { in VisitIfStmt()
[all …]
H A DAttrVisitor.h27 #define PTR(CLASS) typename Ptr<CLASS>::type macro
29 return static_cast<ImplClass *>(this)->Visit##NAME(static_cast<PTR(NAME)>(A))
31 RetTy Visit(PTR(Attr) A) { in Visit()
45 RetTy Visit##NAME##Attr(PTR(NAME##Attr) A) { DISPATCH(Attr); }
48 RetTy VisitAttr(PTR(Attr)) { return RetTy(); } in VisitAttr()
50 #undef PTR
/llvm-project-15.0.7/llvm/test/Instrumentation/AddressSanitizer/
H A Dstack-poisoning-and-lifetime-be.ll53 ; ENTRY-NEXT: store [[TYPE]] -13, [[TYPE]]* [[PTR]], align 1
101 ; ENTRY-UAS-NEXT: store [[TYPE]] 2, [[TYPE]]* [[PTR]], align 1
119 ; ENTRY-UAS-NEXT: store [[TYPE]] 5, [[TYPE]]* [[PTR]], align 1
139 ; ENTRY-UAS-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1
143 ; ENTRY-UAS-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1
174 ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1
179 ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1
184 ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1
189 ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1
194 ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1
[all …]
H A Dstack-poisoning-and-lifetime.ll28 ; ENTRY-NEXT: store [[TYPE]] -235802127, [[TYPE]]* [[PTR]], align 1
53 ; ENTRY-NEXT: store [[TYPE]] -13, [[TYPE]]* [[PTR]], align 1
101 ; ENTRY-UAS-NEXT: store [[TYPE]] 2, [[TYPE]]* [[PTR]], align 1
139 ; ENTRY-UAS-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1
143 ; ENTRY-UAS-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1
174 ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1
179 ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1
184 ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1
189 ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1
194 ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A Dunprofitable-pr.ll14 ; CHECK-NEXT: store volatile i64 1, i64* [[PTR:%.*]], align 4
15 ; CHECK-NEXT: [[PTRINT:%.*]] = ptrtoint i64* [[PTR]] to i64
19 ; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8
20 ; CHECK-NEXT: store volatile i64 3, i64* [[PTR]], align 8
29 ; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8
30 ; CHECK-NEXT: store volatile i64 2, i64* [[PTR]], align 8
66 ; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8
67 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
72 ; CHECK-NEXT: store volatile i64 3, i64* [[PTR]], align 8
81 ; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dannotate-kernel-features-hsa.ll36 ; AKF_HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] {
198 ; HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] {
246 ; HSA-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] {
464 ; HSA-SAME: (i32* [[PTR:%.*]]) #[[ATTR1]] {
476 ; HSA-SAME: (i32* [[PTR:%.*]]) #[[ATTR1]] {
513 ; HSA-SAME: (i32* [[PTR:%.*]]) #[[ATTR1]] {
525 ; HSA-SAME: (i32* [[PTR:%.*]]) #[[ATTR1]] {
537 ; AKF_HSA-SAME: (i8* [[PTR:%.*]]) #[[ATTR1]] {
544 ; ATTRIBUTOR_HSA-SAME: (i8* [[PTR:%.*]]) #[[ATTR11]] {
558 ; AKF_HSA-SAME: (i8* [[PTR:%.*]]) #[[ATTR1]] {
[all …]
H A Dannotate-kernel-features.ll19 ; CHECK-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1:[0-9]+]] {
31 ; AKF_CHECK-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] {
49 ; AKF_CHECK-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] {
73 ; AKF_CHECK-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] {
97 ; AKF_CHECK-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] {
115 ; AKF_CHECK-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] {
193 ; CHECK-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] {
241 ; CHECK-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] {
359 ; CHECK-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] {
371 ; CHECK-SAME: (i32 addrspace(1)* [[PTR:%.*]]) #[[ATTR1]] {
[all …]
H A Dllvm.amdgcn.ds.consume.ll8 ; GCN: s_mov_b32 m0, [[PTR]]
20 ; GCN: s_mov_b32 m0, [[PTR]]
34 ; SI: s_add_i32 [[PTR]], [[PTR]], 16
35 ; SI: s_mov_b32 m0, [[PTR]]
38 ; CIPLUS: s_mov_b32 m0, [[PTR]]
55 ; CIPLUS: s_add_i32 [[PTR]], [[PTR]], 0x10000
57 ; GCN: s_mov_b32 m0, [[PTR]]
82 ; GCN: s_mov_b32 m0, [[PTR]]
94 ; GCN: s_mov_b32 m0, [[PTR]]
116 ; GCN: s_mov_b32 m0, [[PTR]]
[all …]
H A Dllvm.amdgcn.ds.append.ll7 ; GCN: s_load_dword [[PTR:s[0-9]+]]
8 ; GCN: s_mov_b32 m0, [[PTR]]
20 ; GCN: s_mov_b32 m0, [[PTR]]
34 ; SI: s_add_i32 [[PTR]], [[PTR]], 16
35 ; SI: s_mov_b32 m0, [[PTR]]
38 ; CIPLUS: s_mov_b32 m0, [[PTR]]
55 ; CIPLUS-SDAG: s_add_i32 [[PTR]], [[PTR]], 0x10000
88 ; GCN: s_mov_b32 m0, [[PTR]]
100 ; GCN: s_mov_b32 m0, [[PTR]]
122 ; GCN: s_mov_b32 m0, [[PTR]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/
H A Dinlining-alignment-assumptions.ll23 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
24 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
25 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
26 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
27 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
31 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 1, i64* [[PTR]], align 4
39 ; ASSUMPTIONS-ON-NEXT: store volatile i64 0, i64* [[PTR]], align 8
40 ; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
41 ; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
42 ; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
[all …]
/llvm-project-15.0.7/libunwind/src/
H A DUnwindRegistersSave.S72 #define PTR %rcx macro
75 #define PTR %rdi macro
80 movq %rax, (PTR)
81 movq %rbx, 8(PTR)
82 movq %rcx, 16(PTR)
83 movq %rdx, 24(PTR)
84 movq %rdi, 32(PTR)
85 movq %rsi, 40(PTR)
86 movq %rbp, 48(PTR)
87 movq %rsp, 56(PTR)
[all …]
/llvm-project-15.0.7/clang/test/CodeGenOpenCLCXX/
H A Daddress-space-deduction.clcpp1 …nters %s -triple spir-unknown-unknown -O0 -emit-llvm -o - | FileCheck %s -check-prefixes=COMMON,PTR
5 #define PTR &
8 #define PTR *
14 //PTR: @glob_p ={{.*}} addrspace(1) global i32 addrspace(4)* addrspacecast (i32 addrspace(1)* @glob…
16 int PTR glob_p = ADR(glob);
19 //PTR: @_ZZ3fooiPU3AS4iE8loc_st_p = internal addrspace(1) global i32 addrspace(4)* addrspacecast (i…
25 int foo(int par, int PTR par_p){
32 int PTR loc_p = ADR(loc);
34 const __private int PTR loc_p_const = ADR(loc);
38 static int PTR loc_st_p = ADR(loc_st);
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/
H A Duserstack.ll11 ; CHECK: .local i[[PTR]]{{$}}
31 ; CHECK: .local i[[PTR]]{{$}}
51 ; CHECK: .local i[[PTR]]{{$}}
81 ; CHECK: i[[PTR]].const $push[[L2:.+]]=, 48
90 ; CHECK: i[[PTR]].const $push[[OFF:.+]]=, 8
110 ; CHECK: .local i[[PTR]]{{$}}
139 ; CHECK: i[[PTR]].sub
155 ; CHECK: i[[PTR]].sub
184 ; CHECK: i[[PTR]].sub
204 ; CHECK: i[[PTR]].sub
[all …]
H A Dstack-alignment.ll8 ; CHECK-NEXT: i[[PTR]].const $push[[L2:.+]]=, 16
9 ; CHECK-NEXT: i[[PTR]].sub $push[[L10:.+]]=, $pop[[L1]], $pop[[L2]]
17 ; CHECK: i[[PTR]].add $push[[L5:.+]]=, $pop[[M4]], $pop{{.+}}
29 ; CHECK-NEXT: i[[PTR]].const $push[[L2:.+]]=, 32
30 ; CHECK-NEXT: i[[PTR]].sub $push[[L8:.+]]=, $pop[[L9]], $pop[[L2]]
31 ; CHECK-NEXT: i[[PTR]].const $push[[L3:.+]]=, -32
32 ; CHECK-NEXT: i[[PTR]].and $push[[L7:.+]]=, $pop[[L8]], $pop[[L3]]
50 ; CHECK: i[[PTR]].sub $push[[L12:.+]]=, $pop[[L13]], $pop{{.+}}
51 ; CHECK: i[[PTR]].and $push[[L11:.+]]=, $pop[[L12]], $pop{{.+}}
55 ; CHECK: i[[PTR]].add $push[[L6:.+]]=, $pop[[M6]], $pop{{.+}}
[all …]
H A Dload-store-pic.ll14 ; PIC: .globaltype __memory_base, [[PTR]]
24 ; PIC-NEXT: [[PTR]].const $push[[L1:[0-9]+]]=, hidden_global@MBREL{{$}}
25 ; PIC-NEXT: [[PTR]].add $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
38 ; PIC-NEXT: [[PTR]].const $push[[L3:[0-9]+]]=, 20{{$}}
39 ; PIC-NEXT: [[PTR]].add $push[[L4:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
53 ; PIC-NEXT: [[PTR]].const $push[[L1:[0-9]+]]=, hidden_global@MBREL{{$}}
54 ; PIC-NEXT: [[PTR]].add $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
66 ; PIC-NEXT: [[PTR]].add $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
67 ; PIC-NEXT: [[PTR]].const $push[[L3:[0-9]+]]=, 20{{$}}
96 ; PIC-NEXT: [[PTR]].const $push[[L1:[0-9]+]]=, 20{{$}}
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/AtomicExpand/LoongArch/
H A Dload-store-atomic.ll7 ; LA32-NEXT: [[VAL:%.*]] = load atomic i8, ptr [[PTR:%.*]] monotonic, align 1
12 ; LA64-NEXT: [[VAL:%.*]] = load atomic i8, ptr [[PTR:%.*]] monotonic, align 1
22 ; LA32-NEXT: [[VAL:%.*]] = load atomic i16, ptr [[PTR:%.*]] monotonic, align 2
27 ; LA64-NEXT: [[VAL:%.*]] = load atomic i16, ptr [[PTR:%.*]] monotonic, align 2
37 ; LA32-NEXT: [[VAL:%.*]] = load atomic i32, ptr [[PTR:%.*]] monotonic, align 4
67 ; LA32-NEXT: store atomic i8 [[V:%.*]], ptr [[PTR:%.*]] monotonic, align 1
72 ; LA64-NEXT: store atomic i8 [[V:%.*]], ptr [[PTR:%.*]] monotonic, align 1
82 ; LA32-NEXT: store atomic i16 [[V:%.*]], ptr [[PTR:%.*]] monotonic, align 2
87 ; LA64-NEXT: store atomic i16 [[V:%.*]], ptr [[PTR:%.*]] monotonic, align 2
97 ; LA32-NEXT: store atomic i32 [[V:%.*]], ptr [[PTR:%.*]] monotonic, align 4
[all …]
/llvm-project-15.0.7/llvm/test/MC/X86/
H A Dintel-syntax.s79 mov DWORD PTR [RSP - 4], 257
81 mov DWORD PTR [RSP + 4], 258
85 mov BYTE PTR [RSP - 17], 97
87 mov EAX, DWORD PTR [RSP - 4]
89 mov RAX, QWORD PTR [RSP]
93 mov DWORD PTR [RSP - 4], -4
95 mov RCX, QWORD PTR [0]
466 bt DWORD PTR [EAX], 1
467 bt DWORD PTR [EAX], 1
468 bts DWORD PTR [EAX], 1
[all …]
H A Dintel-syntax-x86-64-avx512f_vl.s17 vcmppd k3,xmm27,XMMWORD PTR [rcx],0x7b
25 vcmppd k3,xmm27,QWORD PTR [rcx]{1to2},0x7b
29 vcmppd k3,xmm27,XMMWORD PTR [rdx+0x7f0],0x7b
33 vcmppd k3,xmm27,XMMWORD PTR [rdx+0x800],0x7b
37 vcmppd k3,xmm27,XMMWORD PTR [rdx-0x800],0x7b
41 vcmppd k3,xmm27,XMMWORD PTR [rdx-0x810],0x7b
73 vcmppd k4,ymm17,YMMWORD PTR [rcx],0x7b
81 vcmppd k4,ymm17,QWORD PTR [rcx]{1to4},0x7b
129 vcmpps k4,xmm29,XMMWORD PTR [rcx],0x7b
137 vcmpps k4,xmm29,DWORD PTR [rcx]{1to4},0x7b
[all …]
/llvm-project-15.0.7/compiler-rt/test/asan/TestCases/
H A Ddebug_stacks.cpp9 #define PTR "%llx" macro
11 #define PTR "%lx" macro
44 fprintf(stderr, "0x" PTR "\n", trace[0]); in main()
46 fprintf(stderr, "0x" PTR "\n", trace[1]); in main()
57 fprintf(stderr, "0x" PTR "\n", trace[0]); in main()
59 fprintf(stderr, "0x" PTR "\n", trace[1]); in main()
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cconv/
H A Dreturn-struct.ll191 ; O32-DAG: lw [[T1:\$[0-9]+]], 4([[PTR]])
192 ; O32-DAG: lw [[T2:\$[0-9]+]], 8([[PTR]])
193 ; O32-DAG: lw [[T3:\$[0-9]+]], 12([[PTR]])
194 ; O32-DAG: lw [[T4:\$[0-9]+]], 16([[PTR]])
195 ; O32-DAG: lw [[T5:\$[0-9]+]], 20([[PTR]])
211 ; N32-DAG: lw [[T1:\$[0-9]+]], 4([[PTR]])
212 ; N32-DAG: lw [[T2:\$[0-9]+]], 8([[PTR]])
213 ; N32-DAG: lw [[T3:\$[0-9]+]], 12([[PTR]])
214 ; N32-DAG: lw [[T4:\$[0-9]+]], 16([[PTR]])
226 ; N64-DAG: lw [[T1:\$[0-9]+]], 4([[PTR]])
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dinst-select-load-smrd.mir20 # GCN: [[PTR:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
23 # SICI: S_LOAD_DWORD_IMM [[PTR]], 1, 0
24 # VI: S_LOAD_DWORD_IMM [[PTR]], 4, 0
27 # SICI: S_LOAD_DWORD_IMM [[PTR]], 255, 0
28 # VI: S_LOAD_DWORD_IMM [[PTR]], 1020, 0
32 # SI: S_LOAD_DWORD_SGPR [[PTR]], [[K1024]], 0
33 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 256, 0
34 # VI: S_LOAD_DWORD_IMM [[PTR]], 1024, 0
38 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262143
39 # VI: S_LOAD_DWORD_IMM [[PTR]], 1048572
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dptrtoint-nullgep.ll129 ; LLPARSER-NEXT: [[RET:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
145 ; LLPARSER-NEXT: [[RET:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
161 ; LLPARSER-NEXT: [[RET:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
179 ; LLPARSER-NEXT: [[RET:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
196 ; LLPARSER-NEXT: [[RET:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
220 ; LLPARSER-NEXT: [[RET:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
246 ; LLPARSER-NEXT: [[RET:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
270 ; LLPARSER-NEXT: [[RET:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
297 ; LLPARSER-NEXT: [[RET:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
349 ; LLPARSER-NEXT: [[RET:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i32
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dalloc-no-stack-realign.ll9 ; CHECK: mov r[[PTR:[0-9]+]], r{{[0-9]+}}
12 ; CHECK: add r[[PTR]], r[[PTR]], #32
14 ; CHECK: vld1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[PTR]]:128]
15 ; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[PTR]]:128]
36 ; CHECK: mov r[[PTR:[0-9]+]], r{{[0-9]+}}
39 ; CHECK: add r[[PTR]], r[[PTR]], #32
41 ; CHECK: vld1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[PTR]]:128]
42 ; CHECK: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[PTR]]:128]

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