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Searched refs:P7 (Results 1 – 25 of 37) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Drecipest.ll15 ; CHECK-P7-LABEL: foo_fmf:
16 ; CHECK-P7: # %bb.0:
31 ; CHECK-P7-NEXT: blr
80 ; CHECK-P7-NEXT: blr
103 ; CHECK-P7-NEXT: blr
134 ; CHECK-P7-NEXT: blr
174 ; CHECK-P7-NEXT: blr
211 ; CHECK-P7-NEXT: blr
264 ; CHECK-P7-NEXT: blr
298 ; CHECK-P7-NEXT: blr
[all …]
H A DPR35812-neg-cmpxchg.ll68 ; CHECK-P7-LABEL: main:
70 ; CHECK-P7-NEXT: mflr 0
76 ; CHECK-P7-NEXT: li 7, 0
82 ; CHECK-P7-NEXT: sync
90 ; CHECK-P7-NEXT: #
96 ; CHECK-P7-NEXT: #
106 ; CHECK-P7-NEXT: lwsync
117 ; CHECK-P7-NEXT: nop
129 ; CHECK-P7-NEXT: nop
134 ; CHECK-P7-NEXT: mtlr 0
[all …]
H A Dtest-vector-insert.ll24 ; CHECK-LE-P7-LABEL: test:
39 ; CHECK-LE-P7-NEXT: blr
57 ; CHECK-BE-P7-LABEL: test:
70 ; CHECK-BE-P7-NEXT: blr
93 ; CHECK-LE-P7-LABEL: test2:
108 ; CHECK-LE-P7-NEXT: blr
126 ; CHECK-BE-P7-LABEL: test2:
139 ; CHECK-BE-P7-NEXT: blr
177 ; CHECK-LE-P7-NEXT: blr
208 ; CHECK-BE-P7-NEXT: blr
[all …]
H A Dload-and-splat.ll37 ; P7-LABEL: test:
42 ; P7-NEXT: blr
91 ; P7-LABEL: test2:
97 ; P7-NEXT: blr
148 ; P7-LABEL: test3:
154 ; P7-NEXT: blr
204 ; P7-LABEL: test4:
209 ; P7-NEXT: blr
286 ; P7-NEXT: blr
363 ; P7-NEXT: blr
[all …]
H A Dvector-rotates.ll19 ; CHECK-P7-LABEL: rotl_v16i8:
20 ; CHECK-P7: # %bb.0: # %entry
25 ; CHECK-P7-NEXT: blr
43 ; CHECK-P7-LABEL: rotl_v8i16:
49 ; CHECK-P7-NEXT: blr
67 ; CHECK-P7-LABEL: rotl_v4i32_0:
73 ; CHECK-P7-NEXT: blr
90 ; CHECK-P7-LABEL: rotl_v4i32_1:
96 ; CHECK-P7-NEXT: blr
114 ; CHECK-P7-LABEL: rotl_v2i64:
[all …]
H A Dvavg.ll16 ; CHECK-P7-LABEL: test_v8i16:
19 ; CHECK-P7-NEXT: blr
41 ; CHECK-P7-NEXT: blr
60 ; CHECK-P7-LABEL: test_v4i32:
63 ; CHECK-P7-NEXT: blr
85 ; CHECK-P7-NEXT: blr
107 ; CHECK-P7-NEXT: blr
129 ; CHECK-P7-NEXT: blr
171 ; CHECK-P7-NEXT: blr
202 ; CHECK-P7-NEXT: blr
[all …]
H A Dbitcasts-direct-move.ll10 ; CHECK-P7: stfs 1,
11 ; CHECK-P7: lwa 3,
21 ; CHECK-P7: stfd 1,
22 ; CHECK-P7: ld 3,
30 ; CHECK-P7: stw 3,
31 ; CHECK-P7: lfs 1,
41 ; CHECK-P7: std 3,
42 ; CHECK-P7: lfd 1,
51 ; CHECK-P7: lwz 3,
62 ; CHECK-P7: ld 3,
[all …]
H A Dcanonical-merge-shuffles.ll48 ; CHECK-P7-NEXT: blr
89 ; CHECK-P7-NEXT: blr
123 ; CHECK-P7-NEXT: blr
164 ; CHECK-P7-NEXT: blr
198 ; CHECK-P7-NEXT: blr
239 ; CHECK-P7-NEXT: blr
273 ; CHECK-P7-NEXT: blr
314 ; CHECK-P7-NEXT: blr
348 ; CHECK-P7-NEXT: blr
389 ; CHECK-P7-NEXT: blr
[all …]
H A Dvariable_elem_vec_extracts.ll5 ; RUN: --check-prefix=CHECK-P7
13 ; CHECK-P7-LABEL: @geti
27 ; CHECK-P7-DAG: stxvw4x 34,
28 ; CHECK-P7: lwax 3, 3, [[ELEMOFFREG]]
47 ; CHECK-P7-LABEL: @getl
56 ; CHECK-P7-DAG: stxvd2x 34,
57 ; CHECK-P7: ldx 3, 3, [[ELEMOFFREG]]
71 ; CHECK-P7-LABEL: @getf
79 ; CHECK-P7-DAG: stxvw4x 34,
93 ; CHECK-P7-LABEL: @getd
[all …]
H A Dfp-splat.ll2 …-mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=CHECK-P7 -check-prefix=CHECK
13 ; CHECK-P7-NOT: xscvdpspn
24 ; CHECK-P7: xxspltd
H A Dunaligned.ll133 ; For VSX on P7, unaligned loads and stores are preferable to aligned
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/PowerPC/
H A Dinsert_extract-inseltpoison.ll12 ; CHECK-P7-LABEL: 'insert'
14 ; CHECK-P7-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
34 ; CHECK-P7-LABEL: 'extract'
36 ; CHECK-P7-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 %x
55 ; CHECK-P7-LABEL: 'test2xdouble'
58 ; CHECK-P7-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
81 ; CHECK-P7-LABEL: 'test4xi32'
83 ; CHECK-P7-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
102 ; CHECK-P7-LABEL: 'vexti32'
138 ; CHECK-P7-LABEL: 'vexti64'
[all …]
H A Dinsert_extract.ll12 ; CHECK-P7-LABEL: 'insert'
14 ; CHECK-P7-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
34 ; CHECK-P7-LABEL: 'extract'
36 ; CHECK-P7-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 %x
55 ; CHECK-P7-LABEL: 'test2xdouble'
58 ; CHECK-P7-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
81 ; CHECK-P7-LABEL: 'test4xi32'
83 ; CHECK-P7-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
102 ; CHECK-P7-LABEL: 'vexti32'
138 ; CHECK-P7-LABEL: 'vexti64'
[all …]
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/modernize/
H A Dmake-unique-default-init.cpp56 std::unique_ptr<int[]> P7, P8; in basic() local
57 P7.reset(new int[5]()); in basic()
66 P7.reset(new int[Num]); in basic()
H A Dmake-shared.cpp85 std::shared_ptr<int> P7 = std::shared_ptr<int>((new int)); in basic() local
/llvm-project-15.0.7/libcxx/test/libcxx/utilities/memory/pointer.conversion/
H A Dto_address.pass.cpp68 namespace P7 { namespace
127 P7::CanQual<int>* p7 = nullptr; in test()
129 ASSERT_SAME_TYPE(decltype(std::__to_address(p7)), P7::CanQual<int>*); in test()
/llvm-project-15.0.7/libcxx/test/std/utilities/memory/pointer.conversion/
H A Dto_address.pass.cpp70 namespace P7 { namespace
129 P7::CanQual<int>* p7 = nullptr; in test()
131 ASSERT_SAME_TYPE(decltype(std::to_address(p7)), P7::CanQual<int>*); in test()
/llvm-project-15.0.7/libc/AOR_v20.02/math/
H A Dv_logf.c18 #define P7 v_f32 (Poly[0]) macro
63 p = v_fma_f32 (P7, r2, p); in V_NAME()
/llvm-project-15.0.7/clang/test/Driver/
H A Dhip-phases.hip33 // NRD-DAG: [[P7:[0-9]+]]: assembler, {[[P6]]}, object, (device-[[T]], [[ARCH]])
34 // RDC-DAG: [[P7:[0-9]+]]: backend, {[[P5]]}, ir, (device-[[T]], [[ARCH]])
35 // BIN-DAG: [[P8:[0-9]+]]: linker, {[[P7]]}, image, (device-[[T]], [[ARCH]])
60 // ASM-DAG: [[P7:[0-9]+]]: compiler, {[[P6]]}, ir, (host-[[T]])
61 // ASM-DAG: [[P8:[0-9]+]]: backend, {[[P7]]}, assembler, (host-[[T]])
83 // NRD2-DAG: [[P8:[0-9]+]]: linker, {[[P7]]}, image, (device-[[T]], [[ARCH1]])
154 // ASM2-DAG: [[P7:[0-9]+]]: compiler, {[[P6]]}, ir, (device-[[T]], [[ARCH2]])
229 // DBIN-DAG: [[P7:[0-9]+]]: linker, {[[P6]]}, hip-fatbin, (device-hip, )
298 // DASM2-DAG: [[P7:[0-9]+]]: compiler, {[[P6]]}, ir, (device-[[T]], [[ARCH2]])
339 // RL2-EM-DAG: [[P8:[0-9]+]]: linker, {[[P5]], [[P7]]}, object, (device-[[T]])
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/ConstantMerge/
H A Ddont-merge.ll72 define void @test4(i32** %P1, i32** %P2, i32** %P3, i32** %P4, i32** %P5, i32** %P6, i32** %P7, i32…
79 store i32* @T4D1, i32** %P7
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dremark_extract_broadcast.ll47 %P7 = getelementptr inbounds i16, i16* %ptr, i64 7
63 store i16 %A7, i16* %P7, align 2
/llvm-project-15.0.7/llvm/test/Transforms/ArgumentPromotion/
H A Dmetadata.ll40 …:%.*]], i32** [[P3:%.*]], i32** [[P4:%.*]], i32** [[P5:%.*]], i32** [[P6:%.*]], i32** [[P7:%.*]]) {
47 ; CHECK-NEXT: [[P7_VAL:%.*]] = load i32*, i32** [[P7]], align 8, !nontemporal !4
/llvm-project-15.0.7/llvm/test/FileCheck/
H A Dmissspelled-directive.txt7 RUN: %ProtectFileCheckOutput not FileCheck --check-prefix=P7 %s 2>&1 | FileCheck --check-prefix=CHE…
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCScheduleP7.td1 //===-- PPCScheduleP7.td - PPC P7 Scheduling Definitions ---*- tablegen -*-===//
18 // Scheduling for the P7 involves tracking two types of resources:
384 // P7 machine model for scheduling and other instruction cost heuristics.
/llvm-project-15.0.7/llvm/test/DebugInfo/X86/
H A Dprolog-params.mir131 # CHECK: ![[P7:.*]] = !DILocalVariable(name: "p7"
151 # CHECK-NEXT: DBG_VALUE $rsp, 0, ![[P7]], !DIExpression(DW_OP_plus_uconst, 24)

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