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/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DGISelUtilsTest.cpp72 EXPECT_EQ(P0, getGCDType(P0, S64)); in TEST()
75 EXPECT_EQ(S32, getGCDType(P0, P1)); in TEST()
81 EXPECT_EQ(P0, getGCDType(P0, V2P0)); in TEST()
82 EXPECT_EQ(P0, getGCDType(V2P0, P0)); in TEST()
106 EXPECT_EQ(P0, getGCDType(P0, V2S64)); in TEST()
166 EXPECT_EQ(P0, getLCMType(P0, S64)); in TEST()
168 EXPECT_EQ(P0, getLCMType(S32, P0)); in TEST()
169 EXPECT_EQ(P0, getLCMType(P0, S32)); in TEST()
173 EXPECT_EQ(P0, getLCMType(P0, P0)); in TEST()
176 EXPECT_EQ(P0, getLCMType(P0, P1)); in TEST()
[all …]
H A DGISelAliasTest.cpp27 LLT P0 = LLT::pointer(0, 64); in TEST_F() local
29 auto Base = B.buildIntToPtr(P0, Copies[0]); in TEST_F()
30 auto Base2 = B.buildIntToPtr(P0, Copies[1]); in TEST_F()
32 auto Addr = B.buildPtrAdd(P0, Base, B.buildConstant(S64, 8)); in TEST_F()
79 LLT P0 = LLT::pointer(0, 64); in TEST_F() local
81 auto Base = B.buildIntToPtr(P0, Copies[0]); in TEST_F()
109 LLT P0 = LLT::pointer(0, 64); in TEST_F() local
116 auto GFI1 = B.buildFrameIndex(P0, FI1); in TEST_F()
118 auto GFI2 = B.buildFrameIndex(P0, FI1); in TEST_F()
131 auto GFixedFI1 = B.buildFrameIndex(P0, FixedFI1); in TEST_F()
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/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dcompare-int.ll15 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
24 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
33 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
42 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
51 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
60 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
69 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
78 ; CHECK: selp.u64 %rd{{[0-9]+}}, 1, 0, %p[[P0]]
107 ; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
116 ; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
[all …]
/llvm-project-15.0.7/clang/test/SemaObjC/
H A Dconditional-expr-3.m3 @protocol P0 protocol
10 @interface A <P0>
17 void barP0(id<P0> x);
26 id<P0> l = a;
30 …id<P0> l = x; // expected-warning {{initializing 'id<P0>' with an expression of incompatible type …
46 bar(cond ? (id<P0, P1>) x : a);
50 bar(cond ? a : (id<P0, P1>) x);
53 void f8(int cond, id<P0,P1> x0, id<P0,P2> x1) {
54 …barP0(cond ? x0 : x1); // expected-warning {{incompatible operand types ('id<P0,P1>' and 'id<P0,P2…
57 void f9(int cond, id<P0,P1> x0, id<P0,P2> x1) {
[all …]
H A Dconditional-expr.m47 @protocol P0 protocol
59 @interface A <P0>
74 void f0(id<P0> x) {
78 void f1(int cond, id<P0> x, id<P0> y) {
82 void f2(int cond, id<P0> x, A *y) {
86 void f3(int cond, id<P0> x, B *y) {
102 id f7(int a, id<P0> x, A* p) {
106 int f8(int a, A<P0> *x, A *y) {
112 A<P0> *l1 = (a ? x : y ); // Ok. y is of A<P1> object type and A is qualified by P0.
117 void f10(int a, id<P0> x, id y) {
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H A Dprotocol-implementation-inherited.m4 @protocol P0 protocol
8 @interface A <P0>
13 @interface B0 : A <P0>
22 @protocol P1 <P0>
/llvm-project-15.0.7/clang/test/SemaObjCXX/
H A Dconditional-expr.mm3 @protocol P0 protocol
10 @interface A <P0>
17 void barP0(id<P0> x);
26 id<P0> l = a;
46 bar(cond ? (id<P0, P1>) x : a);
50 bar(cond ? a : (id<P0, P1>) x);
53 void f8(int cond, id<P0,P1> x0, id<P0,P2> x1) {
54 …barP0(cond ? x0 : x1); // expected-warning {{incompatible operand types ('id<P0,P1>' and 'id<P0,P2…
57 void f9(int cond, id<P0,P1> x0, id<P0,P2> x1) {
58 …barP1(cond ? x0 : x1); // expected-warning {{incompatible operand types ('id<P0,P1>' and 'id<P0,P2…
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/llvm-project-15.0.7/llvm/unittests/XRay/
H A DProfileTest.cpp64 Profile P0, P1; in TEST() local
65 EXPECT_FALSE(errorToBool(P0.addBlock( in TEST()
71 P1 = P0; in TEST()
88 Profile P0, P1; in TEST() local
89 EXPECT_FALSE(errorToBool(P0.addBlock( in TEST()
95 P1 = std::move(P0); in TEST()
113 Profile P0, P1; in TEST() local
116 EXPECT_FALSE(errorToBool(P0.addBlock( in TEST()
120 EXPECT_FALSE(errorToBool(P0.addBlock( in TEST()
163 Profile P0, P1; in TEST() local
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/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dv62_all.s122 if (!P0) V0.cur=vmem(R0+#04)
149 if (P0) V0.cur=vmem(R0+#04)
167 if (P0) V0.cur=vmem(R0++M0)
174 if (!P0) V0=vmem(R0+#04)
179 if (!P0) V0=vmem(R0++#03)
184 if (!P0) V0=vmem(R0++M0)
258 if (P0) V0=vmem(R0+#04):nt
268 if (P0) V0=vmem(R0++M0):nt
327 if (P0) V0=vmem(R0+#04)
332 if (P0) V0=vmem(R0++#03)
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H A Dc4_newval.s7 # CHECK: error: register `P0' used with `.new' but not validly modified in the same packet
12 # CHECK: error: register `P0' used with `.new' but not validly modified in the same packet
18 # CHECK: error: register `P0' used with `.new' but not validly modified in the same packet
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Daddsubcarry.ll6 ; CHECK: p[[P0:[0-3]]] = and(p[[P1:[0-9]]],!p[[P1]])
7 ; CHECK: add({{.*}},{{.*}},p[[P0]]):carry
8 ; CHECK: add({{.*}},{{.*}},p[[P0]]):carry
16 ; CHECK: p[[P0:[0-3]]] = or(p[[P1:[0-9]]],!p[[P1]])
17 ; CHECK: sub({{.*}},{{.*}},p[[P0]]):carry
18 ; CHECK: sub({{.*}},{{.*}},p[[P0]]):carry
/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DLowLevelTypeTest.cpp132 const LLT P0 = LLT::pointer(0, 32); in TEST() local
141 const LLT V2P0 = LLT::fixed_vector(2, P0); in TEST()
156 EXPECT_EQ(P0, S32.changeElementType(P0)); in TEST()
157 EXPECT_EQ(S32, P0.changeElementType(S32)); in TEST()
180 const LLT P0 = LLT::pointer(0, 32); in TEST() local
181 const LLT V2P0 = LLT::fixed_vector(2, P0); in TEST()
182 const LLT V3P0 = LLT::fixed_vector(3, P0); in TEST()
225 const LLT P0 = LLT::pointer(0, 32); in TEST() local
226 const LLT V2P0 = LLT::fixed_vector(2, P0); in TEST()
228 EXPECT_DEATH(P0.changeElementSize(64), in TEST()
[all …]
/llvm-project-15.0.7/llvm/unittests/IR/
H A DConstantsTest.cpp246 CHECK(ConstantExpr::getAdd(P0, P0), "add i32 " P0STR ", " P0STR); in TEST()
247 CHECK(ConstantExpr::getAdd(P0, P0, false, true), in TEST()
249 CHECK(ConstantExpr::getAdd(P0, P0, true, true), in TEST()
251 CHECK(ConstantExpr::getSub(P0, P0), "sub i32 " P0STR ", " P0STR); in TEST()
252 CHECK(ConstantExpr::getMul(P0, P0), "mul i32 " P0STR ", " P0STR); in TEST()
253 CHECK(ConstantExpr::getAnd(P0, P0), "and i32 " P0STR ", " P0STR); in TEST()
254 CHECK(ConstantExpr::getOr(P0, P0), "or i32 " P0STR ", " P0STR); in TEST()
255 CHECK(ConstantExpr::getXor(P0, P0), "xor i32 " P0STR ", " P0STR); in TEST()
258 CHECK(ConstantExpr::getShl(P0, P0, false, true), in TEST()
261 CHECK(ConstantExpr::getLShr(P0, P0, true), in TEST()
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/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dextract.ll10 ; CHECK-NEXT: [[P0:%.*]] = getelementptr inbounds double, double* [[PTR:%.*]], i64 0
12 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast double* [[P0]] to <2 x double>*
20 %P0 = getelementptr inbounds double, double* %ptr, i64 0
24 store double %A0, double* %P0, align 4
44 %P0 = getelementptr inbounds double, double* %ptr, i64 1 ; <--- incorrect order
48 store double %A0, double* %P0, align 4
59 ; CHECK-NEXT: [[P0:%.*]] = getelementptr inbounds double, double* [[PTR:%.*]], i64 0
63 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast double* [[P0]] to <2 x double>*
71 %P0 = getelementptr inbounds double, double* %ptr, i64 0
75 store double %A0, double* %P0, align 4
H A Dzext.ll16 ; SSE2-NEXT: [[I0:%.*]] = load i8, i8* [[P0]], align 1
25 ; SLM-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <2 x i8>*
31 ; AVX-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <2 x i8>*
48 ; SSE2-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <4 x i8>*
54 ; SLM-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <4 x i8>*
60 ; AVX-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <4 x i8>*
85 ; SSE2-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <4 x i8>*
91 ; SLM-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <4 x i8>*
97 ; AVX-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <4 x i8>*
128 ; SLM-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <8 x i8>*
[all …]
H A Dzext-inseltpoison.ll16 ; SSE2-NEXT: [[I0:%.*]] = load i8, i8* [[P0]], align 1
25 ; SLM-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <2 x i8>*
31 ; AVX-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <2 x i8>*
48 ; SSE2-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <4 x i8>*
54 ; SLM-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <4 x i8>*
60 ; AVX-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <4 x i8>*
85 ; SSE2-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <4 x i8>*
91 ; SLM-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <4 x i8>*
97 ; AVX-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <4 x i8>*
128 ; SLM-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0:%.*]] to <8 x i8>*
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dno-register-coalescing-in-returnsTwice.mir10 # CHECK: %[[R1:[0-9]+]]:gpr = ADDri %stack.0.P0, 0, 14
35 %P0 = alloca %struct.S37, align 8
36 %0 = bitcast %struct.S37* %P0 to %struct.S18*
40 %1 = bitcast %struct.S37* %P0 to i8*
57 %6 = bitcast %struct.S37* %P0 to i8*
105 STRi12 %5, %stack.0.P0, 72, 14, $noreg
117 %24:gpr = LDRi12 %stack.0.P0, 0, 14, $noreg
118 %25:gpr = LDRi12 %stack.0.P0, 4, 14, $noreg
151 STRi12 %5, %stack.0.P0, 12, 14, $noreg
167 %18:gpr = LDRi12 %stack.0.P0, 0, 14, $noreg
[all …]
/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A D2008-08-25-incompatible-cond-expr.m3 @protocol P0 protocol
5 @interface A <P0>
8 id f0(int a, id<P0> x, A* p) {
H A Dforward-protocol-metadata-symbols.m6 @protocol P0 @end protocol
8 @interface A : NSObject <P0>
17 Protocol *P0 = @protocol(P0);
H A Dprotocols.m25 @protocol P0 protocol
53 Protocol *P0 = @protocol(P0);
59 Pbool([P0 conformsTo: P1]);
60 Pbool([P1 conformsTo: P0]);
/llvm-project-15.0.7/llvm/test/Transforms/LoadStoreVectorizer/
H A Dint_sideeffect.ll11 ; CHECK-NEXT: [[P0:%.*]] = getelementptr float, float* [[P:%.*]], i64 0
12 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[P0]] to <4 x float>*
24 ; CHECK-NEXT: [[TMP7:%.*]] = bitcast float* [[P0]] to <4 x float>*
49 ; CHECK-NEXT: [[P0:%.*]] = getelementptr float, float* [[P:%.*]], i64 0
50 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[P0]] to <4 x float>*
62 ; CHECK-NEXT: [[TMP7:%.*]] = bitcast float* [[P0]] to <4 x float>*
85 ; CHECK-NEXT: [[P0:%.*]] = getelementptr float, float* [[P:%.*]], i64 0
89 ; CHECK-NEXT: [[L0:%.*]] = load float, float* [[P0]], align 16
94 ; CHECK-NEXT: store float [[L0]], float* [[P0]], align 16
124 ; CHECK-NEXT: [[L0:%.*]] = load float, float* [[P0]], align 16
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopUnroll/
H A Dpeel-loop-noalias-scope-decl.ll19 ; CHECK-NEXT: store i8 42, i8* [[P0:%.*]], align 1, !alias.scope !3
22 ; CHECK-NEXT: store i8 42, i8* [[P0]], align 1, !noalias !3
28 ; CHECK-NEXT: store i8 52, i8* [[P0]], align 1, !alias.scope !3
31 ; CHECK-NEXT: store i8 52, i8* [[P0]], align 1, !noalias !3
36 ; CHECK-NEXT: store i8 62, i8* [[P0]], align 1, !alias.scope !3
39 ; CHECK-NEXT: store i8 62, i8* [[P0]], align 1, !noalias !3
58 ; CHECK-NEXT: store i8 42, i8* [[P0]], align 1, !alias.scope !6
61 ; CHECK-NEXT: store i8 42, i8* [[P0]], align 1, !noalias !6
66 ; CHECK-NEXT: store i8 52, i8* [[P0]], align 1, !alias.scope !6
69 ; CHECK-NEXT: store i8 52, i8* [[P0]], align 1, !noalias !6
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/
H A Dint_sideeffect.ll10 ; CHECK-NEXT: [[P0:%.*]] = getelementptr float, float* [[P:%.*]], i64 0
13 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[P0]] to <4 x float>*
15 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[P0]] to <4 x float>*
40 ; CHECK-NEXT: [[P0:%.*]] = getelementptr float, float* [[P:%.*]], i64 0
43 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[P0]] to <4 x float>*
45 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[P0]] to <4 x float>*
/llvm-project-15.0.7/clang/test/OpenMP/
H A Dtarget_map_codegen_18.inc259 // CK19-DAG: [[CP0:%.+]] = bitcast i8** [[P0]] to i32**
287 // CK19-DAG: [[CP0:%.+]] = bitcast i8** [[P0]] to i32**
341 // CK19-DAG: [[CP0:%.+]] = bitcast i8** [[P0]] to i32**
367 // CK19-DAG: [[CP0:%.+]] = bitcast i8** [[P0]] to i32**
393 // CK19-DAG: [[CP0:%.+]] = bitcast i8** [[P0]] to i32**
419 // CK19-DAG: [[CP0:%.+]] = bitcast i8** [[P0]] to i32**
449 // CK19-DAG: [[CP0:%.+]] = bitcast i8** [[P0]] to i32**
481 // CK19-DAG: [[CP0:%.+]] = bitcast i8** [[P0]] to i32**
509 // CK19-DAG: [[CP0:%.+]] = bitcast i8** [[P0]] to i32**
563 // CK19-DAG: [[CP0:%.+]] = bitcast i8** [[P0]] to i32**
[all …]
/llvm-project-15.0.7/clang/test/Driver/
H A Dhip-phases.hip23 // BIN-DAG: [[P0:[0-9]+]]: input, "{{.*}}hip-phases.hip", [[T:hip]], (host-[[T]])
24 // BIN-DAG: [[P1:[0-9]+]]: preprocessor, {[[P0]]}, [[T]]-cpp-output, (host-[[T]])
74 // NRD2-DAG: [[P0:[0-9]+]]: input, "{{.*}}hip-phases.hip", [[T:hip]], (host-[[T]])
75 // NRD2-DAG: [[P1:[0-9]+]]: preprocessor, {[[P0]]}, [[T]]-cpp-output, (host-[[T]])
110 // RCL2-DAG: [[P0:[0-9]+]]: input, "{{.*}}hip-phases.hip", [[T:hip]], (host-[[T]])
111 // RCL2-DAG: [[P1:[0-9]+]]: preprocessor, {[[P0]]}, [[T]]-cpp-output, (host-[[T]])
132 // RC2-DAG: [[P0:[0-9]+]]: input, "{{.*}}hip-phases.hip", [[T:hip]], (host-[[T]])
133 // RC2-DAG: [[P1:[0-9]+]]: preprocessor, {[[P0]]}, [[T]]-cpp-output, (host-[[T]])
328 // L2-DAG: [[P0:[0-9]+]]: input, "{{.*}}obj1.o", object
329 // RL2-DAG: [[P1:[0-9]+]]: clang-offload-unbundler, {[[P0]]}, object
[all …]

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