| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsCCState.h | 104 const SmallVectorImpl<ISD::OutputArg> &Outs, CCAssignFn Fn, in PreAnalyzeCallOperands() argument
110 PreAnalyzeCallOperands(Outs, FuncArgs, Func); in PreAnalyzeCallOperands()
114 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands() argument
118 PreAnalyzeCallOperands(Outs, Fn, FuncArgs, Func); in AnalyzeCallOperands()
119 CCState::AnalyzeCallOperands(Outs, Fn); in AnalyzeCallOperands()
127 void AnalyzeCallOperands(const SmallVectorImpl<MVT> &Outs,
173 PreAnalyzeReturnForF128(Outs); in PreAnalyzeReturn()
174 PreAnalyzeReturnForVectorFloat(Outs); in PreAnalyzeReturn()
177 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeReturn() argument
179 PreAnalyzeReturn(Outs, Fn); in AnalyzeReturn()
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| H A D | MipsCCState.cpp | 99 const SmallVectorImpl<ISD::OutputArg> &Outs) { in PreAnalyzeReturnForF128() argument
101 for (unsigned i = 0; i < Outs.size(); ++i) { in PreAnalyzeReturnForF128()
121 const SmallVectorImpl<ISD::OutputArg> &Outs) { in PreAnalyzeReturnForVectorFloat() argument
122 for (unsigned i = 0; i < Outs.size(); ++i) { in PreAnalyzeReturnForVectorFloat()
123 ISD::OutputArg Out = Outs[i]; in PreAnalyzeReturnForVectorFloat()
144 const SmallVectorImpl<ISD::OutputArg> &Outs, in PreAnalyzeCallOperands() argument
147 for (unsigned i = 0; i < Outs.size(); ++i) { in PreAnalyzeCallOperands()
148 TargetLowering::ArgListEntry FuncArg = FuncArgs[Outs[i].OrigArgIndex]; in PreAnalyzeCallOperands()
153 CallOperandIsFixed.push_back(Outs[i].IsFixed); in PreAnalyzeCallOperands()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCCCState.h | 23 PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs);
57 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands() argument
60 IsFixed.resize(Outs.size(), false); in AnalyzeCallOperands()
61 for (unsigned ValNo = 0, E = Outs.size(); ValNo != E; ++ValNo) in AnalyzeCallOperands()
62 if (Outs[ValNo].IsFixed) in AnalyzeCallOperands()
65 CCState::AnalyzeCallOperands(Outs, Fn); in AnalyzeCallOperands()
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| H A D | PPCCCState.cpp | 17 const SmallVectorImpl<ISD::OutputArg> &Outs) { in PreAnalyzeCallOperands() argument
18 for (const auto &I : Outs) { in PreAnalyzeCallOperands()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | CallingConvLower.cpp | 96 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in CheckReturn() argument
99 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { in CheckReturn()
100 MVT VT = Outs[i].VT; in CheckReturn()
101 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; in CheckReturn()
110 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeReturn() argument
113 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { in AnalyzeReturn()
114 MVT VT = Outs[i].VT; in AnalyzeReturn()
115 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; in AnalyzeReturn()
125 unsigned NumOps = Outs.size(); in AnalyzeCallOperands()
127 MVT ArgVT = Outs[i].VT; in AnalyzeCallOperands()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZCallingConv.h | 65 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands() argument
69 for (unsigned i = 0; i < Outs.size(); ++i) in AnalyzeCallOperands()
70 ArgIsFixed.push_back(Outs[i].IsFixed); in AnalyzeCallOperands()
73 for (unsigned i = 0; i < Outs.size(); ++i) in AnalyzeCallOperands()
74 ArgIsShortVector.push_back(IsShortVectorType(Outs[i].ArgVT)); in AnalyzeCallOperands()
76 CCState::AnalyzeCallOperands(Outs, Fn); in AnalyzeCallOperands()
81 void AnalyzeCallOperands(const SmallVectorImpl<MVT> &Outs,
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| /llvm-project-15.0.7/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.h | 77 const SmallVectorImpl<ISD::OutputArg> &Outs,
80 const SmallVectorImpl<ISD::OutputArg> &Outs,
96 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| H A D | LoongArchISelLowering.cpp | 864 CCState &CCInfo, const SmallVectorImpl<ISD::OutputArg> &Outs, in analyzeOutputArgs() argument
866 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { in analyzeOutputArgs()
867 MVT ArgVT = Outs[i].VT; in analyzeOutputArgs()
924 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall() local
943 analyzeOutputArgs(ArgCCInfo, Outs, CC_LoongArch); in LowerCall()
948 for (auto &Arg : Outs) { in LowerCall()
1045 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { in CanLowerReturn() argument
1048 return Outs.size() <= 2; in CanLowerReturn()
1053 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
1063 analyzeOutputArgs(CCInfo, Outs, CC_LoongArch); in LowerReturn()
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.h | 149 const SmallVectorImpl<ISD::OutputArg> &Outs,
153 const SmallVectorImpl<ISD::OutputArg> &Outs,
158 const SmallVectorImpl<ISD::OutputArg> &Outs,
163 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.h | 95 const SmallVectorImpl<ISD::OutputArg> &Outs,
121 const SmallVectorImpl<ISD::OutputArg> &Outs,
149 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| H A D | LanaiISelLowering.cpp | 409 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall() local
535 return CCInfo.CheckReturn(Outs, RetCC_Lanai32); in CanLowerReturn()
541 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
552 CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32); in LowerReturn()
603 bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerCCCCallTo() argument
621 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg); in LowerCCCCallTo()
624 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast); in LowerCCCCallTo()
626 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32); in LowerCCCCallTo()
634 for (unsigned I = 0, E = Outs.size(); I != E; ++I) { in LowerCCCCallTo()
635 ISD::ArgFlagsTy Flags = Outs[I].Flags; in LowerCCCCallTo()
[all …]
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | CallingConvLower.h | 292 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
298 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
303 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
313 void AnalyzeArguments(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeArguments() argument
315 AnalyzeCallOperands(Outs, Fn); in AnalyzeArguments()
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| /llvm-project-15.0.7/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.h | 144 const SmallVectorImpl<ISD::OutputArg> &Outs,
174 const SmallVectorImpl<ISD::OutputArg> &Outs,
178 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| H A D | MSP430ISelLowering.cpp | 441 const SmallVectorImpl<ISD::OutputArg> &Outs) { in AnalyzeVarArgs() argument
442 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack); in AnalyzeVarArgs()
556 State.AnalyzeReturn(Outs, RetCC_MSP430); in AnalyzeRetResult()
589 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall() local
608 Outs, OutVals, Ins, dl, DAG, InVals); in LowerCall()
731 return CCInfo.CheckReturn(Outs, RetCC_MSP430); in CanLowerReturn()
747 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) in LowerReturn()
755 AnalyzeReturnValues(CCInfo, RVLocs, Outs); in LowerReturn()
807 bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerCCCCallTo() argument
815 AnalyzeArguments(CCInfo, ArgLocs, Outs); in LowerCCCCallTo()
[all …]
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| /llvm-project-15.0.7/llvm/unittests/Analysis/ |
| H A D | TBAATest.cpp | 58 raw_svector_ostream Outs(ErrorMsg); in TEST_F() local
63 EXPECT_TRUE(verifyFunction(*F, &Outs)); in TEST_F()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CallLowering.h | 470 bool checkReturn(CCState &CCInfo, SmallVectorImpl<BaseArgInfo> &Outs,
476 SmallVectorImpl<BaseArgInfo> &Outs,
488 SmallVectorImpl<BaseArgInfo> &Outs, in canLowerReturn() argument
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.h | 63 const SmallVectorImpl<ISD::OutputArg> &Outs,
67 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| H A D | CSKYISelLowering.cpp | 420 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { in CanLowerReturn() argument
423 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg)); in CanLowerReturn()
429 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
438 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg)); in LowerReturn()
500 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall() local
517 ArgCCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, IsVarArg)); in LowerCall()
534 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { in LowerCall()
535 ISD::ArgFlagsTy Flags = Outs[i].Flags; in LowerCall()
565 ISD::ArgFlagsTy Flags = Outs[i].Flags; in LowerCall()
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.h | 164 const SmallVectorImpl<ISD::OutputArg> &Outs,
168 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /llvm-project-15.0.7/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 372 auto &Outs = CLI.Outs; in LowerCall() local
397 CCInfo.AnalyzeCallOperands(Outs, getHasAlu32() ? CC_BPF32 : CC_BPF64); in LowerCall()
401 if (Outs.size() > MaxArgs) in LowerCall()
404 for (auto &Arg : Outs) { in LowerCall()
503 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
521 CCInfo.AnalyzeReturn(Outs, getHasAlu32() ? RetCC_BPF32 : RetCC_BPF64); in LowerReturn()
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| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 265 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall() local
280 CCInfo.AnalyzeCallOperands(Outs, CC_ARC); in LowerCall()
634 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { in CanLowerReturn() argument
637 if (!CCInfo.CheckReturn(Outs, RetCC_ARC)) in CanLowerReturn()
647 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn() argument
665 CCInfo.AnalyzeReturn(Outs, RetCC_ARC); in LowerReturn()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.h | 97 const SmallVectorImpl<ISD::OutputArg> &Outs,
100 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /llvm-project-15.0.7/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.h | 154 const SmallVectorImpl<ISD::OutputArg> &Outs,
221 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.h | 246 const SmallVectorImpl<ISD::OutputArg> &Outs,
273 const SmallVectorImpl<ISD::OutputArg> &Outs,
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.h | 39 SmallVectorImpl<BaseArgInfo> &Outs,
|