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Searched refs:OrigReg (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastPreTileConfig.cpp219 Register OrigReg, MachineOperand *RowMO, in reload() argument
221 int FI = getStackSpaceFor(OrigReg); in reload()
222 const TargetRegisterClass &RC = *MRI->getRegClass(OrigReg); in reload()
261 if (MO.isReg() && MO.getReg() == OrigReg) in reload()
267 LLVM_DEBUG(dbgs() << "Reloading " << printReg(OrigReg, TRI) << " into " in reload()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp555 Register OrigReg = U.getReg(); in colorChain() local
556 U.setReg(Substs[OrigReg]); in colorChain()
560 ToErase.push_back(OrigReg); in colorChain()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTailDuplicator.h101 void addSSAUpdateEntry(Register OrigReg, Register NewReg,
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTailDuplicator.cpp331 void TailDuplicator::addSSAUpdateEntry(Register OrigReg, Register NewReg, in addSSAUpdateEntry() argument
334 SSAUpdateVals.find(OrigReg); in addSSAUpdateEntry()
340 SSAUpdateVals.insert(std::make_pair(OrigReg, Vals)); in addSSAUpdateEntry()
341 SSAUpdateVRs.push_back(OrigReg); in addSSAUpdateEntry()
H A DRegisterBankInfo.cpp464 Register OrigReg = MO.getReg(); in applyDefaultMapping() local
466 LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr)); in applyDefaultMapping()
472 LLT OrigTy = MRI.getType(OrigReg); in applyDefaultMapping()
H A DInlineSpiller.cpp1273 Register OrigReg = OrigLI.reg(); in isSpillCandBB() local
1274 SmallSetVector<Register, 16> &Siblings = Virt2SiblingsMap[OrigReg]; in isSpillCandBB()
H A DSplitKit.cpp326 unsigned OrigReg = VRM.getOriginal(CurLI->reg()); in isOriginalEndpoint() local
327 const LiveInterval &Orig = LIS.getInterval(OrigReg); in isOriginalEndpoint()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp574 Register OrigReg = OrigArg.Regs[0]; in lowerFormalArguments() local
577 BoolArgs.push_back({OrigReg, WideReg}); in lowerFormalArguments()
603 Register OrigReg = KV.first; in lowerFormalArguments() local
606 assert(MRI.getType(OrigReg).getScalarSizeInBits() == 1 && in lowerFormalArguments()
609 OrigReg, MIRBuilder.buildAssertZExt(WideTy, WideReg, 1).getReg(0)); in lowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp4183 const SCEV *OrigReg; member
4186 : LUIdx(LI), Imm(I), OrigReg(R) {} in WorkItem()
4196 OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx in print()
4245 const SCEV *OrigReg = J->second; in GenerateCrossUseConstantOffsets() local
4250 if (!isa<SCEVConstant>(OrigReg) && in GenerateCrossUseConstantOffsets()
4279 WorkItems.push_back(WorkItem(LUIdx, Imm, OrigReg)); in GenerateCrossUseConstantOffsets()
4294 const SCEV *OrigReg = WI.OrigReg; in GenerateCrossUseConstantOffsets() local
4296 Type *IntTy = SE.getEffectiveSCEVType(OrigReg->getType()); in GenerateCrossUseConstantOffsets()
4309 if (F.ScaledReg == OrigReg) { in GenerateCrossUseConstantOffsets()
4338 if (BaseReg != OrigReg) in GenerateCrossUseConstantOffsets()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1680 unsigned OrigReg = OrigOp.Mem.BaseReg; in VerifyAndAdjustOperands() local
1686 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1691 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1693 else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1695 else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1705 if (FinalReg != OrigReg) { in VerifyAndAdjustOperands()