Home
last modified time | relevance | path

Searched refs:Opnd2 (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DReassociate.cpp1353 XorOpnd *Opnd2, APInt &ConstOpnd, in CombineXorOpnd() argument
1356 if (X != Opnd2->getSymbolicPart()) in CombineXorOpnd()
1363 if (Opnd2->getValue()->hasOneUse()) in CombineXorOpnd()
1372 if (Opnd1->isOrExpr() != Opnd2->isOrExpr()) { in CombineXorOpnd()
1373 if (Opnd2->isOrExpr()) in CombineXorOpnd()
1374 std::swap(Opnd1, Opnd2); in CombineXorOpnd()
1377 const APInt &C2 = Opnd2->getConstPart(); in CombineXorOpnd()
1393 const APInt &C2 = Opnd2->getConstPart(); in CombineXorOpnd()
1409 const APInt &C2 = Opnd2->getConstPart(); in CombineXorOpnd()
1418 if (Instruction *T = dyn_cast<Instruction>(Opnd2->getValue())) in CombineXorOpnd()
/llvm-project-15.0.7/llvm/include/llvm/Transforms/Scalar/
H A DReassociate.h115 reassociate::XorOpnd *Opnd2, APInt &ConstOpnd,
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DPatternMatch.h2102 template <typename Opnd0, typename Opnd1, typename Opnd2, typename Opnd3>
2103 inline typename m_Intrinsic_Ty<Opnd0, Opnd1, Opnd2, Opnd3>::Ty
2104 m_MaskedLoad(const Opnd0 &Op0, const Opnd1 &Op1, const Opnd2 &Op2,
2111 inline typename m_Intrinsic_Ty<Opnd0, Opnd1, Opnd2, Opnd3>::Ty
2112 m_MaskedGather(const Opnd0 &Op0, const Opnd1 &Op1, const Opnd2 &Op2,
2192 template <typename Opnd0, typename Opnd1, typename Opnd2>
2193 inline typename m_Intrinsic_Ty<Opnd0, Opnd1, Opnd2>::Ty
2194 m_FShl(const Opnd0 &Op0, const Opnd1 &Op1, const Opnd2 &Op2) {
2198 template <typename Opnd0, typename Opnd1, typename Opnd2>
2199 inline typename m_Intrinsic_Ty<Opnd0, Opnd1, Opnd2>::Ty
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp446 MachineOperand &Opnd2 = DI->getOperand(2); in findInductionRegister() local
448 if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) { in findInductionRegister()
1628 MachineOperand &Opnd2 = DI->getOperand(2); in fixupInductionVariable() local
1630 if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) { in fixupInductionVariable()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp431 MachineOperand &Opnd2 = CurInst->getOperand(3 - I); in searchALUInst() local
433 if (Opnd2.getReg() != AluDest.getReg()) in searchALUInst()
H A DX86ISelLowering.cpp10311 SDValue &Opnd0, SDValue &Opnd1, SDValue &Opnd2, in isFMAddSubOrFMSubAdd() argument
10327 Opnd2 = Opnd1; in isFMAddSubOrFMSubAdd()
10351 SDValue Opnd2; in lowerToAddSubOrFMAddSub() local
10352 if (isFMAddSubOrFMSubAdd(Subtarget, DAG, Opnd0, Opnd1, Opnd2, NumExtracts)) { in lowerToAddSubOrFMAddSub()
10354 return DAG.getNode(Opc, DL, VT, Opnd0, Opnd1, Opnd2); in lowerToAddSubOrFMAddSub()
40672 SDValue Opnd2; in combineShuffleToAddSubOrFMAddSub() local
40673 if (isFMAddSubOrFMSubAdd(Subtarget, DAG, Opnd0, Opnd1, Opnd2, 2)) { in combineShuffleToAddSubOrFMAddSub()
40675 return DAG.getNode(Opc, DL, VT, Opnd0, Opnd1, Opnd2); in combineShuffleToAddSubOrFMAddSub()