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/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DMCInstrDescView.cpp54 bool Operand::isMemory() const { in isMemory()
115 Operand Operand; in create() local
116 Operand.Index = OpIndex; in create()
128 Operand.Info = &OpInfo; in create()
129 Operands.push_back(Operand); in create()
133 Operand Operand; in create() local
134 Operand.Index = OpIndex; in create()
135 Operand.IsDef = true; in create()
142 Operand Operand; in create() local
143 Operand.Index = OpIndex; in create()
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H A DMCInstrDescView.h66 struct Operand { struct
122 const Operand &getPrimaryOperand(const Variable &Var) const;
159 const SmallVector<Operand, 8> Operands;
167 SmallVector<Operand, 8> Operands,
192 RegisterOperandAssignment(const Operand *Operand, MCPhysReg Reg) in RegisterOperandAssignment()
193 : Op(Operand), Reg(Reg) {} in RegisterOperandAssignment()
195 const Operand *Op; // Pointer to an Explicit Register Operand.
/llvm-project-15.0.7/mlir/include/mlir/Dialect/SPIRV/IR/
H A DSPIRVArithmeticOps.td50 let summary = "Floating-point addition of Operand 1 and Operand 2.";
55 The types of Operand 1 and Operand 2 both must be the same as Result
84 The types of Operand 1 and Operand 2 both must be the same as Result
88 if Operand 2 is 0.
117 The types of Operand 1 and Operand 2 both must be the same as Result
276 let summary = "Integer addition of Operand 1 and Operand 2.";
316 let summary = "Integer multiplication of Operand 1 and Operand 2.";
356 let summary = "Integer subtraction of Operand 2 from Operand 1.";
414 Operand 1, member 0 gets 2w + Operand 1 - Operand 2, where w is the
484 of Operand 2.
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H A DSPIRVLogicalOps.td67 The type of Operand 1 and Operand 2 must be a scalar or vector of
101 The type of Operand 1 and Operand 2 must be a scalar or vector of
163 than Operand 2.
361 than Operand 2.
593 if either Operand 1 or Operand 2 are false.
631 false if Operand 1 and Operand 2 have different values.
700 is false if Operand 1 and Operand 2 have the same value.
736 if both Operand 1 and Operand 2 are false.
851 Operand 2.
1060 Operand 2.
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H A DSPIRVBitOps.td313 Result is 1 if both Operand 1 and Operand 2 are 1. Result is 0 if either
314 Operand 1 or Operand 2 are 0.
321 Operand 1 and Operand 2 must be a scalar or vector of integer type.
348 Result is 1 if either Operand 1 or Operand 2 is 1. Result is 0 if both
349 Operand 1 and Operand 2 are 0.
356 Operand 1 and Operand 2 must be a scalar or vector of integer type.
383 Result is 1 if exactly one of Operand 1 or Operand 2 is 1. Result is 0
384 if Operand 1 and Operand 2 have the same value.
391 Operand 1 and Operand 2 must be a scalar or vector of integer type.
546 let summary = "Complement the bits of Operand.";
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/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dexpand-pseudos.ll10 ….v8::internal::Operand" = type { %"class.v8::internal::Register", %"class.v8::internal::Register",…
12 %"union.v8::internal::Operand::Value" = type { i32, [20 x i8] }
15 …%"class.v8::internal::Assembler"*, [1 x i32], [1 x i32], %"class.v8::internal::Operand"*, i32, i32)
19 %5 = alloca %"class.v8::internal::Operand", align 8
21 %7 = bitcast %"class.v8::internal::Operand"* %5 to i8*
22 %8 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
23 %9 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
24 %10 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
25 %11 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
26 …%12 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5, i32 0, i32…
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/llvm-project-15.0.7/llvm/lib/DebugInfo/DWARF/
H A DDWARFExpression.cpp130 for (unsigned Operand = 0; Operand < 2; ++Operand) { in extract() local
141 Operands[Operand] = (int8_t)Operands[Operand]; in extract()
146 Operands[Operand] = (int16_t)Operands[Operand]; in extract()
151 Operands[Operand] = (int32_t)Operands[Operand]; in extract()
162 Operands[Operand] = in extract()
175 assert(Operand == 1); in extract()
192 if (Operand == 0) in extract()
195 Operands[Operand] = Offset; in extract()
283 for (unsigned Operand = 0; Operand < 2; ++Operand) { in print() local
299 assert(Operand == 1); in print()
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonDepOperands.td17 def s6_0Imm : Operand<i32> { let ParserMatchClass = s6_0ImmOperand; let DecoderMethod = "s6_0ImmDec…
20 def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand; let DecoderMethod = "s32_0Imm…
23 def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; let DecoderMethod = "unsigned…
44 def s31_1Imm : Operand<i32> { let ParserMatchClass = s31_1ImmOperand; let DecoderMethod = "s31_1Imm…
53 def s3_0Imm : Operand<i32> { let ParserMatchClass = s3_0ImmOperand; let DecoderMethod = "s3_0ImmDec…
56 def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; let DecoderMethod = "s4_0ImmDec…
59 def s4_1Imm : Operand<i32> { let ParserMatchClass = s4_1ImmOperand; let DecoderMethod = "s4_1ImmDec…
62 def s4_2Imm : Operand<i32> { let ParserMatchClass = s4_2ImmOperand; let DecoderMethod = "s4_2ImmDec…
65 def s4_3Imm : Operand<i32> { let ParserMatchClass = s4_3ImmOperand; let DecoderMethod = "s4_3ImmDec…
68 def s6_3Imm : Operand<i32> { let ParserMatchClass = s6_3ImmOperand; let DecoderMethod = "s6_3ImmDec…
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H A DHexagonOperands.td10 def f32Imm : Operand<f32> { let ParserMatchClass = f32ImmOperand; }
12 def f64Imm : Operand<f64> { let ParserMatchClass = f64ImmOperand; }
15 def s9_0Imm : Operand<i32> { let ParserMatchClass = s9_0ImmOperand; }
17 def s27_2Imm : Operand<i32> { let ParserMatchClass = s27_2ImmOperand; }
27 def u64_0Imm : Operand<i64> { let ParserMatchClass = u64_0ImmOperand; }
29 def n1Const : Operand<i32> { let ParserMatchClass = n1ConstOperand; }
31 def bblabel : Operand<i32>;
/llvm-project-15.0.7/lldb/include/lldb/Core/
H A DDisassembler.h198 struct Operand { struct
207 std::vector<Operand> m_children; argument
215 static Operand BuildRegister(ConstString &r); argument
217 static Operand BuildImmediate(int64_t imm);
218 static Operand BuildDereference(const Operand &ref);
219 static Operand BuildSum(const Operand &lhs, const Operand &rhs);
220 static Operand BuildProduct(const Operand &lhs, const Operand &rhs);
261 std::function<bool(const Instruction::Operand &)>
266 std::function<bool(const Instruction::Operand &)>
270 std::function<bool(const Instruction::Operand &)>
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/llvm-project-15.0.7/lldb/source/Plugins/Disassembler/LLVMC/
H A DDisassemblerLLVMC.cpp736 Operand ret; in ParseRegisterName()
777 Operand ret; in ParseImmediate()
886 Operand product; in ParseIntelIndexedAccess()
891 Operand index; in ParseIntelIndexedAccess()
902 Operand deref; in ParseIntelIndexedAccess()
907 Operand deref; in ParseIntelIndexedAccess()
949 Operand deref; in ParseIntelDerefAccess()
954 Operand deref; in ParseIntelDerefAccess()
995 Operand offset; in ParseARMOffsetAccess()
1000 Operand deref; in ParseARMOffsetAccess()
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/llvm-project-15.0.7/lldb/source/Core/
H A DDisassembler.cpp1208 Operand ret; in BuildRegister()
1216 Operand ret; in BuildImmediate()
1223 Instruction::Operand Instruction::Operand::BuildImmediate(int64_t imm) { in BuildImmediate()
1224 Operand ret; in BuildImmediate()
1236 Instruction::Operand
1237 Instruction::Operand::BuildDereference(const Operand &ref) { in BuildDereference()
1238 Operand ret; in BuildDereference()
1244 Instruction::Operand Instruction::Operand::BuildSum(const Operand &lhs, in BuildSum()
1246 Operand ret; in BuildSum()
1252 Instruction::Operand Instruction::Operand::BuildProduct(const Operand &lhs, in BuildProduct()
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/llvm-project-15.0.7/flang/include/flang/Evaluate/
H A Dexpression.h227 using Operand = A; member
245 using Operand = A;
294 using Operand = A;
301 using Operand = A;
308 using Operand = A;
315 using Operand = A;
322 using Operand = A;
343 Extremum(Ordering ord, Expr<Operand> &&x, Expr<Operand> &&y)
366 using Base = Operation<Concat, Result, Operand, Operand>;
377 using Base = Operation<LogicalOperation, Result, Operand, Operand>;
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrBuilder.h93 unsigned Operand) { in getAddressFromInstr() argument
95 const MachineOperand &Op0 = MI->getOperand(Operand); in getAddressFromInstr()
104 const MachineOperand &Op1 = MI->getOperand(Operand + 1); in getAddressFromInstr()
107 const MachineOperand &Op2 = MI->getOperand(Operand + 2); in getAddressFromInstr()
110 const MachineOperand &Op3 = MI->getOperand(Operand + 3); in getAddressFromInstr()
132 static inline void setDirectAddressInInstr(MachineInstr *MI, unsigned Operand, in setDirectAddressInInstr() argument
135 MI->getOperand(Operand).ChangeToRegister(Reg, /*isDef=*/false); in setDirectAddressInInstr()
136 MI->getOperand(Operand + 1).setImm(1); in setDirectAddressInInstr()
137 MI->getOperand(Operand + 2).setReg(0); in setDirectAddressInInstr()
138 MI->getOperand(Operand + 3).ChangeToImmediate(0); in setDirectAddressInInstr()
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCELFStreamer.cpp139 const MCOperand &Operand = Inst.getOperand(Inst.getNumOperands() - 1); in emitGOTToPCRelReloc() local
140 assert(Operand.isExpr() && "Expecting an MCExpr."); in emitGOTToPCRelReloc()
142 const MCExpr *Expr = Operand.getExpr(); in emitGOTToPCRelReloc()
174 const MCOperand &Operand = Inst.getOperand(Inst.getNumOperands() - 1); in emitGOTToPCRelLabel() local
175 assert(Operand.isExpr() && "Expecting an MCExpr."); in emitGOTToPCRelLabel()
177 const MCExpr *Expr = Operand.getExpr(); in emitGOTToPCRelLabel()
209 const MCOperand &Operand = Inst.getOperand(LastOp); in isPartOfGOTToPCRelPair() local
210 if (!Operand.isExpr()) in isPartOfGOTToPCRelPair()
214 const MCExpr *Expr = Operand.getExpr(); in isPartOfGOTToPCRelPair()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVVMReflect.cpp142 const Value *Operand = cast<Constant>(Str)->getOperand(0); in runNVVMReflect() local
143 if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(Operand)) { in runNVVMReflect()
149 Operand = Initializer; in runNVVMReflect()
152 assert(isa<ConstantDataSequential>(Operand) && in runNVVMReflect()
154 assert(cast<ConstantDataSequential>(Operand)->isCString() && in runNVVMReflect()
157 StringRef ReflectArg = cast<ConstantDataSequential>(Operand)->getAsString(); in runNVVMReflect()
H A DNVPTXGenericToNVVM.cpp108 Value *Operand = II.getOperand(i); in runOnModule() local
109 if (isa<Constant>(Operand)) { in runOnModule()
111 i, remapConstant(&M, &F, cast<Constant>(Operand), Builder)); in runOnModule()
200 Value *Operand = C->getOperand(i); in remapConstantVectorOrConstantAggregate() local
201 Value *NewOperand = remapConstant(M, F, cast<Constant>(Operand), Builder); in remapConstantVectorOrConstantAggregate()
202 OperandChanged |= Operand != NewOperand; in remapConstantVectorOrConstantAggregate()
239 Value *Operand = C->getOperand(i); in remapConstantExpr() local
240 Value *NewOperand = remapConstant(M, F, cast<Constant>(Operand), Builder); in remapConstantExpr()
241 OperandChanged |= Operand != NewOperand; in remapConstantExpr()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td545 def u1imm : Operand<i32> {
555 def u2imm : Operand<i32> {
565 def atimm : Operand<i32> {
575 def u3imm : Operand<i32> {
585 def u4imm : Operand<i32> {
594 def s5imm : Operand<i32> {
701 def s34imm : Operand<i64> {
776 def crbitm: Operand<i8> {
872 def memri : Operand<iPTR> {
879 def memrr : Operand<iPTR> {
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/llvm-project-15.0.7/lldb/source/Target/
H A DStackFrame.cpp1226 std::pair<const Instruction::Operand *, int64_t>
1230 case Instruction::Operand::Type::Dereference: in GetBaseExplainingValue()
1231 case Instruction::Operand::Type::Immediate: in GetBaseExplainingValue()
1232 case Instruction::Operand::Type::Invalid: in GetBaseExplainingValue()
1233 case Instruction::Operand::Type::Product: in GetBaseExplainingValue()
1236 case Instruction::Operand::Type::Sum: { in GetBaseExplainingValue()
1269 case Instruction::Operand::Type::Register: { in GetBaseExplainingValue()
1289 std::pair<const Instruction::Operand *, int64_t>
1346 case Instruction::Operand::Type::Immediate: { in GuessValueForAddress()
1369 case Instruction::Operand::Type::Register: { in GuessValueForAddress()
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/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInfo.td144 def bb_op : Operand<OtherVT>;
147 def local_op : Operand<i32>;
159 def i32imm_op : Operand<i32>;
162 def i64imm_op : Operand<i64>;
186 def table32_op : Operand<i32>;
189 def offset32_op : Operand<i32>;
192 def offset64_op : Operand<i64>;
195 def P2Align : Operand<i32> {
200 def tag_op : Operand<i32>;
205 def Signature : Operand<i32> {
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/llvm-project-15.0.7/mlir/test/IR/
H A Dprint-ir-defuse.mlir12 // CHECK: - Operand produced by operation 'dialect.op1'
13 // CHECK: - Operand produced by operation 'dialect.op1'
16 // CHECK: - Operand produced by Block argument, number 0
17 // CHECK: - Operand produced by operation 'dialect.op1'
/llvm-project-15.0.7/llvm/lib/Target/M68k/AsmParser/
H A DM68kAsmParser.cpp522 if (Operand.isReg() && in validateTargetOperandClass()
530 if (Operand.isReg() && in validateTargetOperandClass()
537 if (Operand.isReg() && in validateTargetOperandClass()
546 if (Operand.isReg() && in validateTargetOperandClass()
553 if (Operand.isReg() && in validateTargetOperandClass()
554 ((Operand.getReg() == M68k::A0) || (Operand.getReg() == M68k::A1))) { in validateTargetOperandClass()
560 if (Operand.isReg() && in validateTargetOperandClass()
561 ((Operand.getReg() == M68k::D0) || (Operand.getReg() == M68k::D1))) { in validateTargetOperandClass()
567 if (Operand.isReg() && in validateTargetOperandClass()
568 ((Operand.getReg() == M68k::D0) || (Operand.getReg() == M68k::D1) || in validateTargetOperandClass()
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/llvm-project-15.0.7/clang/include/clang/AST/
H A DExprCXX.h848 : Expr(CXXTypeidExprClass, Ty, VK_LValue, OK_Ordinary), Operand(Operand), in CXXTypeidExpr()
854 : Expr(CXXTypeidExprClass, Ty, VK_LValue, OK_Ordinary), Operand(Operand), in CXXTypeidExpr()
1185 Stmt *Operand; variable
1228 return child_range(&Operand, Operand ? &Operand + 1 : &Operand); in children()
1232 return const_child_range(&Operand, Operand ? &Operand + 1 : &Operand); in children()
4017 Stmt *Operand; variable
4024 Operand(Operand), Range(Keyword, RParen) { in CXXNoexceptExpr()
4044 child_range children() { return child_range(&Operand, &Operand + 1); } in children()
4047 return const_child_range(&Operand, &Operand + 1); in children()
4713 SubExprs[SubExpr::Operand] = Operand; in CoroutineSuspendExpr()
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/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUInstructionNotation.rst67 Operand Kinds
70 Operand kind indicates which values are accepted by the operand.
86 Operand Tags
89 Operand tags indicate special operand properties.
92 Operand tag Meaning
102 :<type> Operand *type* differs from *type*
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DPseudoLoweringEmitter.cpp27 enum MapKind { Operand, Imm, Reg }; enumerator
30 unsigned Operand; // Operand number mapped to. member
105 OperandMap[BaseIdx + i + I].Kind = OpData::Operand; in addDagOperandMapping()
201 if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand) in evaluateExpansion()
215 OperandMap[Insn.Operands[i].MIOperandNo + I].Data.Operand = in evaluateExpansion()
255 case OpData::Operand: in emitLoweringEmitter()
258 .Operand].MIOperandNo + i in emitLoweringEmitter()

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