| /llvm-project-15.0.7/llvm/tools/llvm-readobj/ |
| H A D | ARMEHABIPrinter.h | 111 uint8_t Opcode0 = Opcodes[OI++ ^ 3]; in Decode_1000iiii_iiiiiiii() local
114 uint16_t GPRMask = (Opcode1 << 4) | ((Opcode0 & 0x0f) << 12); in Decode_1000iiii_iiiiiiii()
158 uint8_t Opcode0 = Opcodes[OI++ ^ 3]; in Decode_10110001_0000iiii() local
161 SW.startLine() << format("0x%02X 0x%02X ; %s", Opcode0, Opcode1, in Decode_10110001_0000iiii()
186 uint8_t Opcode0 = Opcodes[OI++ ^ 3]; in Decode_10110011_sssscccc() local
188 SW.startLine() << format("0x%02X 0x%02X ; pop ", Opcode0, Opcode1); in Decode_10110011_sssscccc()
209 uint8_t Opcode0 = Opcodes[OI++ ^ 3]; in Decode_11000110_sssscccc() local
219 uint8_t Opcode0 = Opcodes[OI++ ^ 3]; in Decode_11000111_0000iiii() local
222 << format("0x%02X 0x%02X ; %s", Opcode0, Opcode1, in Decode_11000111_0000iiii()
230 uint8_t Opcode0 = Opcodes[OI++ ^ 3]; in Decode_11001000_sssscccc() local
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.h | 244 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
|
| H A D | X86TargetTransformInfo.cpp | 5358 bool X86TTIImpl::isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, in isLegalAltInstr() argument
5375 unsigned Opc = OpcodeMask.test(Lane) ? Opcode1 : Opcode0; in isLegalAltInstr()
|
| H A D | X86ISelLowering.cpp | 38742 unsigned Opcode0 = BC0.getOpcode(); in canonicalizeShuffleMaskWithHorizOp() local
38744 return V.getOpcode() != Opcode0 || V.getValueType() != VT0; in canonicalizeShuffleMaskWithHorizOp()
38748 bool isHoriz = (Opcode0 == X86ISD::FHADD || Opcode0 == X86ISD::HADD || in canonicalizeShuffleMaskWithHorizOp()
38749 Opcode0 == X86ISD::FHSUB || Opcode0 == X86ISD::HSUB); in canonicalizeShuffleMaskWithHorizOp()
38750 bool isPack = (Opcode0 == X86ISD::PACKSS || Opcode0 == X86ISD::PACKUS); in canonicalizeShuffleMaskWithHorizOp()
38785 if (Src1.getOpcode() == Opcode0 && Src0->isOnlyUserOf(Src1.getNode())) in canonicalizeShuffleMaskWithHorizOp()
38794 SDValue LHS = DAG.getNode(Opcode0, DL, SrcVT, M0, M1); in canonicalizeShuffleMaskWithHorizOp()
38795 SDValue RHS = DAG.getNode(Opcode0, DL, SrcVT, M2, M3); in canonicalizeShuffleMaskWithHorizOp()
38796 return DAG.getNode(Opcode0, DL, VT0, LHS, RHS); in canonicalizeShuffleMaskWithHorizOp()
38826 SDValue Res = DAG.getNode(Opcode0, DL, VT0, LHS, RHS); in canonicalizeShuffleMaskWithHorizOp()
[all …]
|
| /llvm-project-15.0.7/llvm/include/llvm/Analysis/ |
| H A D | TargetTransformInfo.h | 696 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1611 virtual bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0,
2041 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isLegalAltInstr() argument
2043 return Impl.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); in isLegalAltInstr()
|
| H A D | TargetTransformInfoImpl.h | 282 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isLegalAltInstr() argument
|
| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | TargetTransformInfo.cpp | 418 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, in isLegalAltInstr() argument
420 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask); in isLegalAltInstr()
|
| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 2403 unsigned Opcode0 = C.Op0.getOpcode(); in shouldSwapCmpOperands() local
2404 if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND) in shouldSwapCmpOperands()
2406 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND) in shouldSwapCmpOperands()
2409 Opcode0 == ISD::AND && in shouldSwapCmpOperands()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 5064 unsigned Opcode0 = isSignedMinMax(N0, N1, N2, N3, CC); in isSaturatingMinMax() local
5065 if (!Opcode0) in isSaturatingMinMax()
5099 if (!Opcode1 || Opcode0 == Opcode1) in isSaturatingMinMax()
5102 ConstantSDNode *MinCOp = isConstOrConstSplat(Opcode0 == ISD::SMIN ? N1 : N01); in isSaturatingMinMax()
5103 ConstantSDNode *MaxCOp = isConstOrConstSplat(Opcode0 == ISD::SMIN ? N01 : N1); in isSaturatingMinMax()
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 3744 unsigned Opcode0 = TE->getOpcode(); in reorderTopToBottom() local
3752 if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) { in reorderTopToBottom()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 13811 unsigned Opcode0 = SUB->getOperand(0).getOpcode(); in performVecReduceAddCombineWithUADDLP() local
13820 if (Opcode0 == ISD::ZERO_EXTEND && Opcode1 == ISD::ZERO_EXTEND) { in performVecReduceAddCombineWithUADDLP()
13822 } else if (Opcode0 == ISD::SIGN_EXTEND && Opcode1 == ISD::SIGN_EXTEND) { in performVecReduceAddCombineWithUADDLP()
|