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/llvm-project-15.0.7/llvm/test/CodeGen/SPIRV/transcoding/
H A Dfcmp.ll3 ; CHECK-SPIRV: OpName %[[#r1:]] "r1"
4 ; CHECK-SPIRV: OpName %[[#r2:]] "r2"
5 ; CHECK-SPIRV: OpName %[[#r3:]] "r3"
6 ; CHECK-SPIRV: OpName %[[#r4:]] "r4"
7 ; CHECK-SPIRV: OpName %[[#r5:]] "r5"
8 ; CHECK-SPIRV: OpName %[[#r6:]] "r6"
9 ; CHECK-SPIRV: OpName %[[#r7:]] "r7"
10 ; CHECK-SPIRV: OpName %[[#r8:]] "r8"
11 ; CHECK-SPIRV: OpName %[[#r9:]] "r9"
12 ; CHECK-SPIRV: OpName %[[#r10:]] "r10"
[all …]
H A DOpVectorExtractDynamic.ll3 ; CHECK-SPIRV: OpName %[[#vec:]] "vec"
4 ; CHECK-SPIRV: OpName %[[#index:]] "index"
5 ; CHECK-SPIRV: OpName %[[#res:]] "res"
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp235 {R600::OpName::src0, R600::OpName::src0_sel}, in getSelIdx()
236 {R600::OpName::src1, R600::OpName::src1_sel}, in getSelIdx()
237 {R600::OpName::src2, R600::OpName::src2_sel}, in getSelIdx()
238 {R600::OpName::src0_X, R600::OpName::src0_sel_X}, in getSelIdx()
239 {R600::OpName::src0_Y, R600::OpName::src0_sel_Y}, in getSelIdx()
240 {R600::OpName::src0_Z, R600::OpName::src0_sel_Z}, in getSelIdx()
241 {R600::OpName::src0_W, R600::OpName::src0_sel_W}, in getSelIdx()
245 {R600::OpName::src1_W, R600::OpName::src1_sel_W} in getSelIdx()
286 {R600::OpName::src0, R600::OpName::src0_sel}, in getSrcs()
287 {R600::OpName::src1, R600::OpName::src1_sel}, in getSrcs()
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H A DSIPeepholeSDWA.cpp346 TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers); in convertToSDWA()
350 Src = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in convertToSDWA()
364 TII->getNamedOperand(MI, AMDGPU::OpName::dst_unused); in convertToSDWA()
899 .add(*TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) in pseudoOpConvertToVOP2()
900 .add(*TII->getNamedOperand(MI, AMDGPU::OpName::src0)) in pseudoOpConvertToVOP2()
901 .add(*TII->getNamedOperand(MI, AMDGPU::OpName::src1)) in pseudoOpConvertToVOP2()
908 .add(*TII->getNamedOperand(MISucc, AMDGPU::OpName::vdst)) in pseudoOpConvertToVOP2()
909 .add(*TII->getNamedOperand(MISucc, AMDGPU::OpName::src0)) in pseudoOpConvertToVOP2()
910 .add(*TII->getNamedOperand(MISucc, AMDGPU::OpName::src1)) in pseudoOpConvertToVOP2()
942 (TII->hasModifiersSet(MI, AMDGPU::OpName::clamp) || in isConvertibleToSDWA()
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H A DGCNDPPCombine.cpp135 if (!hasNoImmOrEqual(MI, AMDGPU::OpName::src0_modifiers, 0, Mask) || in isShrinkable()
136 !hasNoImmOrEqual(MI, AMDGPU::OpName::src1_modifiers, 0, Mask) || in isShrinkable()
137 !hasNoImmOrEqual(MI, AMDGPU::OpName::clamp, 0) || in isShrinkable()
138 !hasNoImmOrEqual(MI, AMDGPU::OpName::omod, 0)) { in isShrinkable()
271 AMDGPU::OpName::src0_modifiers) != -1) { in createDPPInst()
275 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in createDPPInst()
295 AMDGPU::OpName::src1_modifiers) != -1) { in createDPPInst()
299 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst()
318 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in createDPPInst()
454 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst()
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H A DR600ExpandSpecialInstrs.cpp86 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction()
93 R600::OpName::pred_sel); in runOnMachineFunction()
95 R600::OpName::pred_sel); in runOnMachineFunction()
117 TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1); in runOnMachineFunction()
204 int Src1Idx = TII->getOperandIdx(MI, R600::OpName::src1); in runOnMachineFunction()
262 SetFlagInNewMI(NewMI, &MI, R600::OpName::clamp); in runOnMachineFunction()
263 SetFlagInNewMI(NewMI, &MI, R600::OpName::literal); in runOnMachineFunction()
264 SetFlagInNewMI(NewMI, &MI, R600::OpName::src0_abs); in runOnMachineFunction()
265 SetFlagInNewMI(NewMI, &MI, R600::OpName::src1_abs); in runOnMachineFunction()
266 SetFlagInNewMI(NewMI, &MI, R600::OpName::src0_neg); in runOnMachineFunction()
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H A DSILoadStoreOptimizer.cpp699 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::addr); in setMI()
702 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sbase); in setMI()
705 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc); in setMI()
711 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr); in setMI()
807 unsigned OperandsToMatch[] = {AMDGPU::OpName::cpol, AMDGPU::OpName::d16, in dmasksCanBeCombined()
808 AMDGPU::OpName::unorm, AMDGPU::OpName::da, in dmasksCanBeCombined()
809 AMDGPU::OpName::r128, AMDGPU::OpName::a16}; in dmasksCanBeCombined()
1189 TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeWrite2Pair()
1191 TII->getNamedOperand(*CI.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
1193 TII->getNamedOperand(*Paired.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
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H A DR600ClauseMergePass.cpp79 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
86 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
92 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in cleanPotentialDisabledCFAlu()
111 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in mergeIfPossible()
123 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); in mergeIfPossible()
125 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); in mergeIfPossible()
127 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); in mergeIfPossible()
139 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE1); in mergeIfPossible()
141 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK1); in mergeIfPossible()
143 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR1); in mergeIfPossible()
H A DSIFoldOperands.cpp165 AMDGPU::OpName::saddr); in frameIndexMayFold()
170 AMDGPU::OpName::vaddr); in frameIndexMayFold()
199 ModIdx = AMDGPU::OpName::src0_modifiers; in updateOperand()
201 ModIdx = AMDGPU::OpName::src1_modifiers; in updateOperand()
203 ModIdx = AMDGPU::OpName::src2_modifiers; in updateOperand()
1314 if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) in isClamp()
1443 TII->hasModifiersSet(MI, AMDGPU::OpName::omod) || in isOMod()
1444 TII->hasModifiersSet(MI, AMDGPU::OpName::clamp)) in isOMod()
1466 !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp) && in isOMod()
1467 !TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) in isOMod()
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H A DR600Packetizer.cpp81 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); in getPreviousVector()
84 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector()
126 R600::OpName::src0, in substitutePV()
127 R600::OpName::src1, in substitutePV()
128 R600::OpName::src2 in substitutePV()
182 int OpI = TII->getOperandIdx(MII->getOpcode(), R600::OpName::pred_sel), in isLegalToPacketizeTogether()
183 OpJ = TII->getOperandIdx(MIJ->getOpcode(), R600::OpName::pred_sel); in isLegalToPacketizeTogether()
217 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), R600::OpName::last); in setIsLastBit()
298 R600::OpName::bank_swizzle); in addToPacket()
302 TII->getOperandIdx(MI.getOpcode(), R600::OpName::bank_swizzle); in addToPacket()
H A DSIInstrInfo.cpp90 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName); in nodesHaveSameOperandValue()
91 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); in nodesHaveSameOperandValue()
380 getNamedOperand(LdSt, AMDGPU::OpName::offset); in getMemOperandsWithOffsetWidth()
383 getNamedOperand(LdSt, AMDGPU::OpName::soffset); in getMemOperandsWithOffsetWidth()
2891 AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers,
2892 AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::clamp,
2893 AMDGPU::OpName::omod};
3834 !hasModifiersSet(MI, AMDGPU::OpName::clamp); in canShrink()
4648 if (!isAlignedReg(AMDGPU::OpName::data0)) { in verifyInstruction()
4656 if (!isAlignedReg(AMDGPU::OpName::vaddr)) { in verifyInstruction()
[all …]
H A DR600ISelLowering.cpp292 TII->setImmOperand(*NewMI, R600::OpName::src0_sel, in EmitInstrWithCustomInserter()
1961 TII->getOperandIdx(Opcode, R600::OpName::src0), in FoldOperand()
1962 TII->getOperandIdx(Opcode, R600::OpName::src1), in FoldOperand()
1963 TII->getOperandIdx(Opcode, R600::OpName::src2), in FoldOperand()
1964 TII->getOperandIdx(Opcode, R600::OpName::src0_X), in FoldOperand()
1965 TII->getOperandIdx(Opcode, R600::OpName::src0_Y), in FoldOperand()
1971 TII->getOperandIdx(Opcode, R600::OpName::src1_W) in FoldOperand()
2078 TII->getOperandIdx(Opcode, R600::OpName::src1_W) in PostISelFolding()
2124 TII->getOperandIdx(Opcode, R600::OpName::src0), in PostISelFolding()
2125 TII->getOperandIdx(Opcode, R600::OpName::src1), in PostISelFolding()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SPIRV/instructions/
H A Dfcmp.ll5 ; CHECK-DAG: OpName [[UEQ:%.*]] "test_ueq"
6 ; CHECK-DAG: OpName [[OEQ:%.*]] "test_oeq"
7 ; CHECK-DAG: OpName [[UNE:%.*]] "test_une"
8 ; CHECK-DAG: OpName [[ONE:%.*]] "test_one"
9 ; CHECK-DAG: OpName [[ULT:%.*]] "test_ult"
10 ; CHECK-DAG: OpName [[OLT:%.*]] "test_olt"
11 ; CHECK-DAG: OpName [[ULE:%.*]] "test_ule"
12 ; CHECK-DAG: OpName [[OLE:%.*]] "test_ole"
13 ; CHECK-DAG: OpName [[UGT:%.*]] "test_ugt"
14 ; CHECK-DAG: OpName [[OGT:%.*]] "test_ogt"
[all …]
H A Dinteger-casts.ll5 ; CHECK-DAG: OpName [[TRUNC32_16:%.*]] "i32toi16"
6 ; CHECK-DAG: OpName [[TRUNC32_8:%.*]] "i32toi8"
7 ; CHECK-DAG: OpName [[TRUNC16_8:%.*]] "i16toi8"
8 ; CHECK-DAG: OpName [[SEXT8_32:%.*]] "s8tos32"
9 ; CHECK-DAG: OpName [[SEXT8_16:%.*]] "s8tos16"
10 ; CHECK-DAG: OpName [[SEXT16_32:%.*]] "s16tos32"
11 ; CHECK-DAG: OpName [[ZEXT8_32:%.*]] "u8tou32"
12 ; CHECK-DAG: OpName [[ZEXT8_16:%.*]] "u8tou16"
13 ; CHECK-DAG: OpName [[ZEXT16_32:%.*]] "u16tou32"
18 ; CHECK-DAG: OpName [[SEXT8_32v4:%.*]] "s8tos32v4"
[all …]
H A Dfloat-casts.ll5 ; CHECK-DAG: OpName [[TRUNC32_16:%.*]] "f32tof16"
6 ; CHECK-DAG: OpName [[EXT16_32:%.*]] "f16tof32"
8 ; CHECK-DAG: OpName [[TRUNC32_16v3:%.*]] "f32tof16v3"
9 ; CHECK-DAG: OpName [[EXT16_32v3:%.*]] "f16tof32v3"
11 ; CHECK-DAG: OpName [[F32toS32:%.*]] "f32tos32"
12 ; CHECK-DAG: OpName [[F32toS16:%.*]] "f32tos16"
13 ; CHECK-DAG: OpName [[F32toS8:%.*]] "f32tos8"
14 ; CHECK-DAG: OpName [[F16toS32:%.*]] "f16tos32"
15 ; CHECK-DAG: OpName [[F16toS16:%.*]] "f16tos16"
16 ; CHECK-DAG: OpName [[F16toS8:%.*]] "f16tos8"
[all …]
H A Dicmp.ll5 ; CHECK-DAG: OpName [[EQ:%.*]] "test_eq"
6 ; CHECK-DAG: OpName [[NE:%.*]] "test_ne"
7 ; CHECK-DAG: OpName [[ULT:%.*]] "test_ult"
8 ; CHECK-DAG: OpName [[SLT:%.*]] "test_slt"
9 ; CHECK-DAG: OpName [[ULE:%.*]] "test_ule"
10 ; CHECK-DAG: OpName [[SLE:%.*]] "test_sle"
11 ; CHECK-DAG: OpName [[UGT:%.*]] "test_ugt"
12 ; CHECK-DAG: OpName [[SGT:%.*]] "test_sgt"
13 ; CHECK-DAG: OpName [[UGE:%.*]] "test_uge"
14 ; CHECK-DAG: OpName [[SGE:%.*]] "test_sge"
[all …]
H A Dptrcmp.ll5 ; CHECK-DAG: OpName [[EQ:%.*]] "test_eq"
6 ; CHECK-DAG: OpName [[NE:%.*]] "test_ne"
7 ; CHECK-DAG: OpName [[ULT:%.*]] "test_ult"
8 ; CHECK-DAG: OpName [[SLT:%.*]] "test_slt"
9 ; CHECK-DAG: OpName [[ULE:%.*]] "test_ule"
10 ; CHECK-DAG: OpName [[SLE:%.*]] "test_sle"
11 ; CHECK-DAG: OpName [[UGT:%.*]] "test_ugt"
12 ; CHECK-DAG: OpName [[SGT:%.*]] "test_sgt"
13 ; CHECK-DAG: OpName [[UGE:%.*]] "test_uge"
14 ; CHECK-DAG: OpName [[SGE:%.*]] "test_sge"
H A Datomic_seq.ll5 ; CHECK-DAG: OpName [[ADD:%.*]] "test_add"
6 ; CHECK-DAG: OpName [[SUB:%.*]] "test_sub"
7 ; CHECK-DAG: OpName [[MIN:%.*]] "test_min"
8 ; CHECK-DAG: OpName [[MAX:%.*]] "test_max"
9 ; CHECK-DAG: OpName [[UMIN:%.*]] "test_umin"
10 ; CHECK-DAG: OpName [[UMAX:%.*]] "test_umax"
11 ; CHECK-DAG: OpName [[AND:%.*]] "test_and"
12 ; CHECK-DAG: OpName [[OR:%.*]] "test_or"
13 ; CHECK-DAG: OpName [[XOR:%.*]] "test_xor"
H A Datomic_acqrel.ll5 ; CHECK-DAG: OpName [[ADD:%.*]] "test_add"
6 ; CHECK-DAG: OpName [[SUB:%.*]] "test_sub"
7 ; CHECK-DAG: OpName [[MIN:%.*]] "test_min"
8 ; CHECK-DAG: OpName [[MAX:%.*]] "test_max"
9 ; CHECK-DAG: OpName [[UMIN:%.*]] "test_umin"
10 ; CHECK-DAG: OpName [[UMAX:%.*]] "test_umax"
11 ; CHECK-DAG: OpName [[AND:%.*]] "test_and"
12 ; CHECK-DAG: OpName [[OR:%.*]] "test_or"
13 ; CHECK-DAG: OpName [[XOR:%.*]] "test_xor"
H A Datomic.ll5 ; CHECK-DAG: OpName [[ADD:%.*]] "test_add"
6 ; CHECK-DAG: OpName [[SUB:%.*]] "test_sub"
7 ; CHECK-DAG: OpName [[MIN:%.*]] "test_min"
8 ; CHECK-DAG: OpName [[MAX:%.*]] "test_max"
9 ; CHECK-DAG: OpName [[UMIN:%.*]] "test_umin"
10 ; CHECK-DAG: OpName [[UMAX:%.*]] "test_umax"
11 ; CHECK-DAG: OpName [[AND:%.*]] "test_and"
12 ; CHECK-DAG: OpName [[OR:%.*]] "test_or"
13 ; CHECK-DAG: OpName [[XOR:%.*]] "test_xor"
H A Dvector-floating-point-arithmetic.ll3 ; CHECK-DAG: OpName [[VECTOR_FNEG:%.+]] "vector_fneg"
4 ; CHECK-DAG: OpName [[VECTOR_FADD:%.+]] "vector_fadd"
5 ; CHECK-DAG: OpName [[VECTOR_FSUB:%.+]] "vector_fsub"
6 ; CHECK-DAG: OpName [[VECTOR_FMUL:%.+]] "vector_fmul"
7 ; CHECK-DAG: OpName [[VECTOR_FDIV:%.+]] "vector_fdiv"
8 ; CHECK-DAG: OpName [[VECTOR_FREM:%.+]] "vector_frem"
H A Dscalar-integer-arithmetic.ll3 ; CHECK-DAG: OpName [[SCALAR_ADD:%.+]] "scalar_add"
4 ; CHECK-DAG: OpName [[SCALAR_SUB:%.+]] "scalar_sub"
5 ; CHECK-DAG: OpName [[SCALAR_MUL:%.+]] "scalar_mul"
6 ; CHECK-DAG: OpName [[SCALAR_UDIV:%.+]] "scalar_udiv"
7 ; CHECK-DAG: OpName [[SCALAR_SDIV:%.+]] "scalar_sdiv"
H A Dvector-integer-arithmetic.ll3 ; CHECK-DAG: OpName [[VECTOR_ADD:%.+]] "vector_add"
4 ; CHECK-DAG: OpName [[VECTOR_SUB:%.+]] "vector_sub"
5 ; CHECK-DAG: OpName [[VECTOR_MUL:%.+]] "vector_mul"
6 ; CHECK-DAG: OpName [[VECTOR_UDIV:%.+]] "vector_udiv"
7 ; CHECK-DAG: OpName [[VECTOR_SDIV:%.+]] "vector_sdiv"
/llvm-project-15.0.7/llvm/test/CodeGen/SPIRV/function/
H A Dtrivial-function-with-attributes.ll8 ; CHECK-DAG: OpName [[FN1:%.+]] "fn1"
9 ; CHECK-DAG: OpName [[FN2:%.+]] "fn2"
10 ; CHECK-DAG: OpName [[FN3:%.+]] "fn3"
11 ; CHECK-DAG: OpName [[FN4:%.+]] "fn4"
12 ; CHECK-DAG: OpName [[FN5:%.+]] "fn5"
13 ; CHECK-DAG: OpName [[FN6:%.+]] "fn6"
14 ; CHECK-DAG: OpName [[FN7:%.+]] "fn7"
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp617 AMDGPU::OpName::cpol); in getInstruction()
694 AMDGPU::OpName::vdst_in); in getInstruction()
743 AMDGPU::OpName::sdst); in convertSDWAInst()
766 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, in collectVOPModifiers()
803 AMDGPU::OpName::op_sel); in convertDPP8Inst()
826 AMDGPU::OpName::op_sel); in convertVOP3DPPInst()
984 AMDGPU::OpName::op_sel); in convertVOP3PDPPInst()
988 AMDGPU::OpName::op_sel_hi); in convertVOP3PDPPInst()
992 AMDGPU::OpName::neg_lo); in convertVOP3PDPPInst()
996 AMDGPU::OpName::neg_hi); in convertVOP3PDPPInst()
[all …]

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