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Searched refs:Op2Reg (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CmovConversion.cpp825 Register Op2Reg = MIIt->getOperand(2).getReg(); in convertCmovInstsToBranches() local
831 std::swap(Op1Reg, Op2Reg); in convertCmovInstsToBranches()
837 auto Op2Itr = RegRewriteTable.find(Op2Reg); in convertCmovInstsToBranches()
839 Op2Reg = Op2Itr->second.second; in convertCmovInstsToBranches()
847 .addReg(Op2Reg) in convertCmovInstsToBranches()
854 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in convertCmovInstsToBranches()
H A DX86InstructionSelector.cpp1487 const Register Op2Reg = I.getOperand(2).getReg(); in selectDivRem() local
1490 assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) && in selectDivRem()
1593 !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) || in selectDivRem()
1636 .addReg(Op2Reg); in selectDivRem()
H A DX86InstrInfo.cpp2381 Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg(); in findThreeSrcCommutedOpIndices() local
2393 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg()) in findThreeSrcCommutedOpIndices()
H A DX86ISelLowering.cpp34672 Register Op2Reg = MIIt->getOperand(2).getReg(); in createPHIsForCMOVsInSinkBB() local
34678 std::swap(Op1Reg, Op2Reg); in createPHIsForCMOVsInSinkBB()
34683 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end()) in createPHIsForCMOVsInSinkBB()
34684 Op2Reg = RegRewriteTable[Op2Reg].second; in createPHIsForCMOVsInSinkBB()
34689 .addReg(Op2Reg) in createPHIsForCMOVsInSinkBB()
34693 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in createPHIsForCMOVsInSinkBB()
34832 Register Op2Reg = FirstCMOV.getOperand(2).getReg(); in EmitLoweredCascadedSelect() local
34837 .addReg(Op2Reg) in EmitLoweredCascadedSelect()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp3115 Register Op2Reg = MIIt->getOperand(2).getReg(); in EmitLoweredSelect() local
3121 std::swap(Op1Reg, Op2Reg); in EmitLoweredSelect()
3126 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end()) in EmitLoweredSelect()
3127 Op2Reg = RegRewriteTable[Op2Reg].second; in EmitLoweredSelect()
3133 .addReg(Op2Reg) in EmitLoweredSelect()
3137 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in EmitLoweredSelect()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1630 unsigned Op2Reg = 0; in SelectSelect() local
1632 Op2Reg = getRegForValue(I->getOperand(2)); in SelectSelect()
1633 if (Op2Reg == 0) return false; in SelectSelect()
1657 Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1); in SelectSelect()
1661 .addReg(Op2Reg) in SelectSelect()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp7224 Register Op2Reg = MI.getOperand(3).getReg(); in lowerSelect() local
7258 auto NewOp2 = MIRBuilder.buildAnd(MaskTy, Op2Reg, NotMask); in lowerSelect()