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Searched refs:NumSubRegs (Results 1 – 3 of 3) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp83 unsigned NumSubRegs; member
1460 if (i == NumSubRegs) { in buildSpillLoadStore()
1691 SB.NumSubRegs == 1 in spillSGPR()
1718 if (SB.NumSubRegs > 1) in spillSGPR()
1742 SB.NumSubRegs == 1 in spillSGPR()
1763 if (SB.NumSubRegs > 1) { in spillSGPR()
1803 SB.NumSubRegs == 1 in restoreSGPR()
1837 SB.NumSubRegs == 1 in restoreSGPR()
1884 SB.NumSubRegs == 1 in spillEmergencySGPR()
1897 if (SB.NumSubRegs > 1) { in spillEmergencySGPR()
[all …]
H A DSIInstrInfo.cpp5499 unsigned NumSubRegs = RegSize / 32; in emitLoadSRsrcFromVGPRLoop() local
5500 assert(NumSubRegs % 2 == 0 && NumSubRegs <= 32 && "Unhandled register size"); in emitLoadSRsrcFromVGPRLoop()
5502 for (unsigned Idx = 0; Idx < NumSubRegs; Idx += 2) { in emitLoadSRsrcFromVGPRLoop()
5530 if (NumSubRegs <= 2) in emitLoadSRsrcFromVGPRLoop()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp329 const MCInstrDesc &MCID, unsigned int NumSubRegs, in copyPhysSubRegs() argument
334 for (unsigned Idx = 0; Idx != NumSubRegs; ++Idx) { in copyPhysSubRegs()
394 unsigned int NumSubRegs = 2; in copyPhysReg() local
396 NumSubRegs, SubRegIdx, &getRegisterInfo()); in copyPhysReg()
400 unsigned int NumSubRegs = 2; in copyPhysReg() local
402 NumSubRegs, SubRegIdx, &getRegisterInfo()); in copyPhysReg()