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Searched refs:NumRegisters (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Support/
H A DARMWinEH.cpp16 uint8_t NumRegisters = RF.Reg(); in SavedRegisterMask() local
36 VFPMask |= (((1 << ((NumRegisters + 1) % 8)) - 1) << 8); in SavedRegisterMask()
38 GPRMask |= (((1 << (NumRegisters + 1)) - 1) << 4); in SavedRegisterMask()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp296 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT); in set() local
298 for (unsigned i = 0; i != NumRegisters; ++i) in set()
300 PHIReg += NumRegisters; in set()
571 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT); in getValueFromVirtualReg() local
572 for (unsigned i = 0, e = NumRegisters; i != e; ++i) in getValueFromVirtualReg()
H A DSelectionDAGBuilder.cpp10714 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); in HandlePHINodesInSuccessorBlocks() local
10715 for (unsigned i = 0, e = NumRegisters; i != e; ++i) in HandlePHINodesInSuccessorBlocks()
10718 Reg += NumRegisters; in HandlePHINodesInSuccessorBlocks()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1468 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT, in computeRegisterProperties() local
1470 NumRegistersForVT[i] = NumRegisters; in computeRegisterProperties()
1471 assert(NumRegistersForVT[i] == NumRegisters && in computeRegisterProperties()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2483 unsigned NumRegisters; in getRegisterTypeForCallingConv() local
2484 std::tie(RegisterVT, NumRegisters) = in getRegisterTypeForCallingConv()
2514 unsigned NumRegisters; in getNumRegistersForCallingConv() local
2515 std::tie(RegisterVT, NumRegisters) = in getNumRegistersForCallingConv()
2518 return NumRegisters; in getNumRegistersForCallingConv()