Searched refs:NextOp (Results 1 – 5 of 5) sorted by relevance
315 auto NextOp = ExprCursor.peek(); in addMachineRegExpression() local316 if (SubRegisterSizeInBits && NextOp && in addMachineRegExpression()317 (NextOp->getOp() != dwarf::DW_OP_LLVM_fragment)) in addMachineRegExpression()383 auto NextOp = ExprCursor.peek(); in addMachineRegExpression() local384 if (SubRegisterSizeInBits && NextOp && in addMachineRegExpression()385 (NextOp->getOp() != dwarf::DW_OP_LLVM_fragment)) in addMachineRegExpression()
280 unsigned NextOp = HasLane ? 5 : 4; in ExpandFPMLxInstruction() local281 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm(); in ExpandFPMLxInstruction()282 Register PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction()
867 MachineOperand *NextOp = findSingleRegUse(Sdst, MRI); in pseudoOpConvertToVOP2() local868 if (!NextOp) in pseudoOpConvertToVOP2()870 MachineInstr &MISucc = *NextOp->getParent(); in pseudoOpConvertToVOP2()
14035 SDValue NextOp = N->getOperand(i); in combineElementTruncationToVectorTruncation() local14036 if (NextOp.getOpcode() != PPCISD::MFVSR) in combineElementTruncationToVectorTruncation()14038 unsigned NextConversion = NextOp.getOperand(0).getOpcode(); in combineElementTruncationToVectorTruncation()14045 if (Is32Bit && !isFPExtLoad(NextOp.getOperand(0).getOperand(0))) in combineElementTruncationToVectorTruncation()
8832 unsigned NextOp = N0.getOpcode(); in visitRotate() local8836 if (NextOp == ISD::ROTL || NextOp == ISD::ROTR) { in visitRotate()8841 bool SameSide = (N->getOpcode() == NextOp); in visitRotate()