| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | and-sext-combine.ll | 4 ; This tests exerts the folding of `VT = (and (sign_extend NarrowVT to
5 ; VT) #bitmask)` into `VT = (zero_extend NarrowVT to VT)` when
7 ; of type NarrowVT inside the value of type VT. The folding is
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 4186 EVT NarrowVT = Node->getMemoryVT(); in lowerATOMIC_LOAD_OP() local
4188 if (NarrowVT == WideVT) in lowerATOMIC_LOAD_OP()
4191 int64_t BitSize = NarrowVT.getSizeInBits(); in lowerATOMIC_LOAD_OP()
4239 NarrowVT, MMO); in lowerATOMIC_LOAD_OP()
4301 EVT NarrowVT = Node->getMemoryVT(); in lowerATOMIC_CMP_SWAP() local
4302 EVT WideVT = NarrowVT == MVT::i64 ? MVT::i64 : MVT::i32; in lowerATOMIC_CMP_SWAP()
4303 if (NarrowVT == WideVT) { in lowerATOMIC_CMP_SWAP()
4307 DL, Tys, Ops, NarrowVT, MMO); in lowerATOMIC_CMP_SWAP()
4319 int64_t BitSize = NarrowVT.getSizeInBits(); in lowerATOMIC_CMP_SWAP()
4342 VTList, Ops, NarrowVT, MMO); in lowerATOMIC_CMP_SWAP()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 8294 if (Op1.getValueType() != NarrowVT) in combineADDSUB_VLToVWADDSUB_VL()
8321 MVT NarrowVT = Op1.getSimpleValueType(); in combineVWADD_W_VL_VWSUB_W_VL() local
8322 unsigned NarrowSize = NarrowVT.getScalarSizeInBits(); in combineVWADD_W_VL_VWSUB_W_VL()
8346 if (Op0.getValueType() != NarrowVT) in combineVWADD_W_VL_VWSUB_W_VL()
8378 Op0 = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, NarrowVT, in combineVWADD_W_VL_VWSUB_W_VL()
8379 DAG.getUNDEF(NarrowVT), Op0, VL); in combineVWADD_W_VL_VWSUB_W_VL()
8462 Op1 = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, NarrowVT, in combineMUL_VLToVWMUL_VL()
8463 DAG.getUNDEF(NarrowVT), Op1, VL); in combineMUL_VLToVWMUL_VL()
8471 if (Op0.getValueType() != NarrowVT) in combineMUL_VLToVWMUL_VL()
8472 Op0 = DAG.getNode(ExtOpc, DL, NarrowVT, Op0, Mask, VL); in combineMUL_VLToVWMUL_VL()
[all …]
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 9168 EVT NarrowVT = LeftOp.getOperand(0).getValueType(); in combineShiftToMULH() local
9180 NarrowVT); in combineShiftToMULH()
10914 EVT NarrowVT = LHS.getValueType(); in visitVSELECT() local
21544 EVT NarrowVT = N->getValueType(0); in foldExtractSubvectorFromShuffleVector() local
21646 return DAG.getUNDEF(NarrowVT); in foldExtractSubvectorFromShuffleVector()
21653 !TLI.isShuffleMaskLegal(NewMask, NarrowVT)) in foldExtractSubvectorFromShuffleVector()
21672 NewOps.emplace_back(DAG.getUNDEF(NarrowVT)); in foldExtractSubvectorFromShuffleVector()
23609 EVT NarrowVT = X.getValueType(); in SimplifyVBinOp() local
23610 if (NarrowVT == Y.getValueType() && in SimplifyVBinOp()
23637 EVT NarrowVT = LHS.getOperand(0).getValueType(); in SimplifyVBinOp() local
[all …]
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| H A D | LegalizeVectorTypes.cpp | 5212 EVT NarrowVT = ((ScalarBits0 < ScalarBits1) ? VT0 : VT1); in WidenVSELECTMask() local
5213 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0); in WidenVSELECTMask()
5216 else if (ScalarBits_ToMask <= NarrowVT.getScalarSizeInBits()) in WidenVSELECTMask()
5217 MaskVT = NarrowVT; in WidenVSELECTMask()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2118 EVT NarrowVT = N->getOperand(0)->getValueType(0); in tryBitfieldExtractOpFromSExt() local
2119 if (VT != MVT::i64 || NarrowVT != MVT::i32) in tryBitfieldExtractOpFromSExt()
2131 unsigned Imms = NarrowVT.getSizeInBits() - 1; in tryBitfieldExtractOpFromSExt()
2146 EVT NarrowVT = Extract.getValueType(); in tryHighFPExt() local
2147 if ((VT != MVT::v2f64 || NarrowVT != MVT::v2f32) && in tryHighFPExt()
2148 (VT != MVT::v4f32 || NarrowVT != MVT::v4f16)) in tryHighFPExt()
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| H A D | AArch64ISelLowering.cpp | 11706 EVT NarrowVT = getPackedSVEVectorVT(VT.getVectorElementCount()); in LowerINSERT_SUBVECTOR() local
11711 Vec0 = getSVESafeBitCast(NarrowVT, Vec0, DAG); in LowerINSERT_SUBVECTOR()
11724 Narrow = DAG.getNode(AArch64ISD::UZP1, DL, NarrowVT, Vec1, HiVec0); in LowerINSERT_SUBVECTOR()
11729 Narrow = DAG.getNode(AArch64ISD::UZP1, DL, NarrowVT, LoVec0, Vec1); in LowerINSERT_SUBVECTOR()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 983 MVT NarrowVT = VT == MVT::v32i16 ? MVT::v16i16 : MVT::v32i8; in PreprocessISelDAG() local
986 CurDAG->getNode(X86ISD::VBROADCAST, dl, NarrowVT, N->getOperand(0)); in PreprocessISelDAG()
1007 MVT NarrowVT = VT == MVT::v32i16 ? MVT::v16i16 : MVT::v32i8; in PreprocessISelDAG() local
1010 SDVTList VTs = CurDAG->getVTList(NarrowVT, MVT::Other); in PreprocessISelDAG()
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| H A D | X86ISelLowering.cpp | 11288 MVT NarrowVT = MVT::getVectorVT(EltVT, 4); in LowerBUILD_VECTOR() local
11291 DAG.getBuildVector(NarrowVT, dl, Ops)); in LowerBUILD_VECTOR()
47443 EVT NarrowVT = Narrow.getValueType(); in PromoteMaskArithmetic() local
47454 return DAG.getZeroExtendInReg(Op, DL, NarrowVT); in PromoteMaskArithmetic()
47457 Op, DAG.getValueType(NarrowVT)); in PromoteMaskArithmetic()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 9608 EVT NarrowVT = EVT::getIntegerVT(*DAG.getContext(), Bits); in performAndCombine() local
9610 DAG.getValueType(NarrowVT)); in performAndCombine()
|