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/llvm-project-15.0.7/mlir/test/Dialect/SPIRV/IR/
H A Dtarget-and-abi.mlir124 // CHECK-SAME: NVIDIA,
126 spv.target_env = #spv.target_env<#spv.vce<v1.0, [], []>, NVIDIA, #spv.resource_limits<>>
/llvm-project-15.0.7/openmp/libomptarget/
H A DREADME.txt41 * CUDA(R) enabled 64-bit NVIDIA(R) GPU architectures
/llvm-project-15.0.7/polly/test/GPGPU/
H A Dlibdevice-functions-copied-into-kernel.ll8 ; be mapped to NVIDIA's libdevice
/llvm-project-15.0.7/openmp/libomptarget/cmake/Modules/
H A DLibomptargetGetDependencies.cmake17 # CUDA : required to control offloading to NVIDIA GPUs.
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DLangStandards.def204 LANGSTANDARD(cuda, "cuda", CUDA, "NVIDIA CUDA(tm)",
/llvm-project-15.0.7/llvm/docs/
H A DCompileCudaWithLLVM.rst30 `NVIDIA's CUDA installation guide
37 NVIDIA's `.run` package and specify its location via `--cuda-path=...` argument.
527 64-bit integer divides are much slower than 32-bit ones on NVIDIA GPUs.
H A DDocker.rst144 <https://github.com/NVIDIA/nvidia-docker>`_ to run your docker containers. Note
H A DNVPTXUsage.rst569 an explicit address space specifier. What is address space 1? NVIDIA GPU
H A DCodeGenerator.rst2246 the NVIDIA NVPTX code generator for LLVM. It is contributed by NVIDIA and is
2252 the official NVIDIA toolchain.
/llvm-project-15.0.7/llvm/include/llvm/ADT/
H A DTriple.h172 NVIDIA, enumerator
/llvm-project-15.0.7/llvm/lib/Support/
H A DTriple.cpp191 case NVIDIA: return "nvidia"; in getVendorTypeName()
539 .Case("nvidia", Triple::NVIDIA) in parseVendor()
/llvm-project-15.0.7/clang/docs/CommandGuide/
H A Dclang.rst230 NVIDIA CUDA(tm)
/llvm-project-15.0.7/llvm/lib/Linker/
H A DIRMover.cpp1555 bool SrcHasLibDeviceTriple = (SrcTriple.getVendor() == Triple::NVIDIA && in run()
/llvm-project-15.0.7/llvm/test/tools/llvm-readobj/ELF/
H A Dfile-header-machine-types.test436 # RUN: llvm-readelf --file-headers %t.cuda.o | FileCheck %s -DMACHINE="NVIDIA CUDA architecture"
/llvm-project-15.0.7/mlir/docs/Dialects/
H A DSPIR-V.md825 spirv-vendor-id ::= `AMD` | `NVIDIA` | ...
/llvm-project-15.0.7/mlir/include/mlir/Dialect/SPIRV/IR/
H A DSPIRVBase.td296 def SPV_V_NVIDIA : I32EnumAttrCase<"NVIDIA", 5>;