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Searched refs:NOR (Results 1 – 22 of 22) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dinstalias-imm-expanding.s344 # MIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
347 # MICROMIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
351 # MIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
354 # MICROMIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
358 # MIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
361 # MICROMIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
365 # MIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
368 # MICROMIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
372 # MIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
375 # MICROMIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.def52 FUSION_OP_SET(AND, AND8, OR, OR8, NAND, NAND8, NOR, NOR8))
56 FUSION_OP_SET(AND, ANDC, EQV, NAND, NOR, OR, ORC, XOR, AND8,
62 FUSION_OP_SET(AND, ANDC, EQV, NAND, NOR, OR, ORC, XOR, AND8,
64 FUSION_OP_SET(AND, ANDC, EQV, NAND, NOR, OR, ORC, XOR, AND8,
H A DPPCBack2BackFusion.def140 NOR,
674 NOR,
H A DP10InstrResources.td1011 NOR, NOR8,
H A DP9InstrResources.td147 (instregex "NOR(8)?(_rec)?$"),
H A DPPCInstrInfo.td2230 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
2259 def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>;
2958 // Implement the 'not' operation with the NOR instruction.
2960 (NOR $in, $in)>;
H A DPPCISelDAGToDAG.cpp3091 ToExtend = SDValue(CurDAG->getMachineNode(Is32Bit ? PPC::NOR : PPC::NOR8, in getCompoundZeroComparisonInGPR()
4369 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0); in trySETCC()
H A DPPCInstr64Bit.td1813 // Implement the 'not' operation with the NOR instruction.
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsExpandPseudo.cpp445 BuildMI(loopMBB, DL, TII->get(Mips::NOR), BinOpRes) in expandAtomicBinOpSubword()
639 unsigned NOR = 0; in expandAtomicBinOp() local
666 NOR = Mips::NOR; in expandAtomicBinOp()
689 NOR = Mips::NOR64; in expandAtomicBinOp()
787 assert(AND && NOR && in expandAtomicBinOp()
790 BuildMI(loopMBB, DL, TII->get(NOR), Scratch).addReg(ZERO).addReg(Scratch); in expandAtomicBinOp()
H A DMips32r6InstrInfo.td1048 defm S : Cmp_Pats<f32, NOR, ZERO>, ISA_MIPS32R6;
1049 defm D : Cmp_Pats<f64, NOR, ZERO>, ISA_MIPS32R6;
H A DMipsScheduleP5600.td41 def : InstRW<[P5600WriteALU], (instrs AND, LUi, NOR, OR, SLTi, SLTiu, SUB,
H A DMipsInstrInfo.td2076 def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>,
2789 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>, ISA_MIPS1;
2792 (NOR GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>, ISA_MIPS1;
3236 (NOR GPR32Opnd:$in, ZERO)>, ISA_MIPS1;
H A DMipsScheduleGeneric.td49 NOR, OR, ORi, ROTR, ROTRV, SEB, SEH, SLL,
H A DMipsISelLowering.cpp1803 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); in emitAtomicBinaryPartword()
1990 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); in emitAtomicCmpSwapPartword()
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dnot-01.ll65 ; NOR 32-bit.
75 ; NOR 64-bit.
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dbitwise.mir224 ; MIPS32: [[NOR:%[0-9]+]]:gpr32 = NOR [[COPY]], $zero
225 ; MIPS32: $v0 = COPY [[NOR]]
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsInstPrinter.cpp317 case Mips::NOR: in printAlias()
/llvm-project-15.0.7/llvm/test/CodeGen/LoongArch/
H A D3r.mir95 $r4 = NOR $r5, $r4
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td315 def NOR : ALU_3R<0b00000000000101000, "nor">;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedNeoverseN2.td1521 (instregex "^(AND|BIC|EOR|NAND|NOR|ORN|ORR)_PPzPP$")>;
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.td1355 // NOR.
/llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4792 FinalOpcode = Mips::NOR; in expandAliasImmediate()