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/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp5069 ISD::CondCode N0CC; in isSaturatingMinMax() local
5075 N0CC = N0.getOpcode() == ISD::SMIN ? ISD::SETLT : ISD::SETGT; in isSaturatingMinMax()
5082 N0CC = cast<CondCodeSDNode>(N0.getOperand(4))->get(); in isSaturatingMinMax()
5092 N0CC = cast<CondCodeSDNode>(N0.getOperand(0).getOperand(2))->get(); in isSaturatingMinMax()
5098 unsigned Opcode1 = isSignedMinMax(N00, N01, N02, N03, N0CC); in isSaturatingMinMax()
5408 SDValue LL, LR, RL, RR, N0CC, N1CC; in foldLogicOfSetCCs() local
5409 if (!isSetCCEquivalent(N0, LL, LR, N0CC) || in foldLogicOfSetCCs()
5430 ISD::CondCode CC0 = cast<CondCodeSDNode>(N0CC)->get(); in foldLogicOfSetCCs()