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Searched refs:MulVal (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineCompares.cpp5094 static Instruction *processUMulZExtIdiom(ICmpInst &I, Value *MulVal, in processUMulZExtIdiom() argument
5099 if (!isa<IntegerType>(MulVal->getType())) in processUMulZExtIdiom()
5102 assert(I.getOperand(0) == MulVal || I.getOperand(1) == MulVal); in processUMulZExtIdiom()
5104 auto *MulInstr = dyn_cast<Instruction>(MulVal); in processUMulZExtIdiom()
5132 if (MulVal->hasNUsesOrMore(2)) in processUMulZExtIdiom()
5133 for (User *U : MulVal->users()) { in processUMulZExtIdiom()
5171 if (ValToMask != MulVal) in processUMulZExtIdiom()
5249 if (MulVal->hasNUsesOrMore(2)) { in processUMulZExtIdiom()
5251 for (User *U : make_early_inc_range(MulVal->users())) { in processUMulZExtIdiom()
5287 if (I.getOperand(0) == MulVal) in processUMulZExtIdiom()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp2325 SDValue MulVal = N.getOperand(0); in matchAddressRecursively() local
2331 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() && in matchAddressRecursively()
2332 isa<ConstantSDNode>(MulVal.getOperand(1))) { in matchAddressRecursively()
2333 Reg = MulVal.getOperand(0); in matchAddressRecursively()
2335 cast<ConstantSDNode>(MulVal.getOperand(1)); in matchAddressRecursively()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4810 APInt MulVal = APInt(BitWidth, 1) << ShiftAmt; in TryMULWIDECombine() local
4811 RHS = DCI.DAG.getConstant(MulVal, DL, MulType); in TryMULWIDECombine()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2440 auto MulVal = B.buildFMul(Ty, SrcReg, OneOver2Pi, Flags); in legalizeSinCos() local
2442 .addUse(MulVal.getReg(0)) in legalizeSinCos()
H A DSIISelLowering.cpp9275 SDValue MulVal = DAG.getNode(ISD::FMUL, DL, VT, Arg, OneOver2Pi, Flags); in LowerTrig() local
9276 TrigVal = DAG.getNode(AMDGPUISD::FRACT, DL, VT, MulVal, Flags); in LowerTrig()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp14260 SDValue MulVal = DAG.getNode(ISD::MUL, DL, VT, N1, MulOper); in performMulCombine() local
14261 return DAG.getNode(AddSubOpc, DL, VT, N1, MulVal); in performMulCombine()
14265 SDValue MulVal = DAG.getNode(ISD::MUL, DL, VT, N0, MulOper); in performMulCombine() local
14266 return DAG.getNode(AddSubOpc, DL, VT, N0, MulVal); in performMulCombine()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp4119 APInt MulVal; in visitMUL() local
4121 if (ISD::isConstantSplatVector(N1.getNode(), MulVal)) { in visitMUL()
4123 APInt NewStep = C0 * MulVal; in visitMUL()