| /llvm-project-15.0.7/llvm/include/llvm/Support/ |
| H A D | Parallel.h | 85 RandomAccessIterator Mid = Start + (std::distance(Start, End) / 2); in medianOf3() local
87 ? (Comp(*Mid, *(End - 1)) ? (Comp(*Start, *Mid) ? Mid : Start) in medianOf3()
89 : (Comp(*Mid, *Start) ? (Comp(*(End - 1), *Mid) ? Mid : End - 1) in medianOf3()
|
| /llvm-project-15.0.7/llvm/tools/bugpoint/ |
| H A D | ListReducer.h | 119 unsigned Mid = MidTop / 2; in reduceList() local
120 std::vector<ElTy> Prefix(TheList.begin(), TheList.begin() + Mid); in reduceList()
121 std::vector<ElTy> Suffix(TheList.begin() + Mid, TheList.end()); in reduceList()
147 MidTop = Mid; in reduceList()
|
| /llvm-project-15.0.7/libcxx/test/libcxx/fuzzing/ |
| H A D | random.pass.cpp | 57 auto Mid = Beg + ((End - Beg) / 2); in DispatchAndCreate() local
59 assert(Mid - Beg <= (End - Mid)); in DispatchAndCreate()
60 ParamT p(Beg, Mid, Mid); in DispatchAndCreate()
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Utils/ |
| H A D | LowerSwitch.cpp | 253 unsigned Mid = Size / 2; in SwitchConvert() local
254 std::vector<CaseRange> LHS(Begin, Begin + Mid); in SwitchConvert()
256 std::vector<CaseRange> RHS(Begin + Mid, End); in SwitchConvert()
259 CaseRange &Pivot = *(Begin + Mid); in SwitchConvert()
|
| /llvm-project-15.0.7/clang/test/CodeGenObjCXX/ |
| H A D | arc-attrs-abi.mm | 25 // ext param info for `id` to `Mid`. Itanium-only check since MSABI seems to
|
| /llvm-project-15.0.7/clang/test/SemaCXX/ |
| H A D | constant-expression-cxx11.cpp | 1130 template<int N> struct Mid : Base {}; struct
1131 struct Derived : Mid<0>, Mid<1> {};
1132 static_assert(&Mid<0>::n == &Mid<1>::n, "");
1133 static_assert((int Derived::*)(int Mid<0>::*)&Mid<0>::n !=
1134 (int Derived::*)(int Mid<1>::*)&Mid<1>::n, "");
1135 static_assert(&Mid<0>::n == (int Mid<0>::*)&Base::n, "");
|
| H A D | conditional-expr.cpp | 33 struct Mid : Base {}; struct
34 struct Fin : Mid, Derived {};
|
| /llvm-project-15.0.7/clang-tools-extra/clang-tidy/readability/ |
| H A D | IdentifierNamingCheck.cpp | 1062 StringRef Mid = StringRef(Fixed).trim("_"); in fixupWithStyle() local
1063 if (Mid.empty()) in fixupWithStyle()
1064 Mid = "_"; in fixupWithStyle()
1066 return (Style.Prefix + HungarianPrefix + Mid + Style.Suffix).str(); in fixupWithStyle()
|
| /llvm-project-15.0.7/llvm/tools/llvm-profdata/ |
| H A D | llvm-profdata.cpp | 427 unsigned Mid = Contexts.size() / 2; in mergeInstrProfile() local
429 assert(Mid > 0 && "Expected more than one context"); in mergeInstrProfile()
431 for (unsigned I = 0; I < Mid; ++I) in mergeInstrProfile()
433 Contexts[I + Mid].get()); in mergeInstrProfile()
440 End = Mid; in mergeInstrProfile()
441 Mid /= 2; in mergeInstrProfile()
442 } while (Mid > 0); in mergeInstrProfile()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | StackColoring.cpp | 1343 auto Mid = FirstS.begin() + OldSize; in runOnMachineFunction() local
1344 std::inplace_merge(FirstS.begin(), Mid, FirstS.end()); in runOnMachineFunction()
|
| H A D | RDFLiveness.cpp | 658 auto ClearIn = [] (RegisterRef RR, const RegisterAggr &Mid, SubMap &SM) { in computePhiInfo() argument
659 if (Mid.empty()) in computePhiInfo()
664 RegisterRef S = Mid.clearIn(RR); in computePhiInfo()
|
| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 2854 const auto &Mid = Indices.begin() + Indices.size() / 2; in lowerVECTOR_SHUFFLE_PCKEV() local
2857 if (fitsRegularPattern<int>(Begin, 1, Mid, 0, 2)) in lowerVECTOR_SHUFFLE_PCKEV()
2859 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size(), 2)) in lowerVECTOR_SHUFFLE_PCKEV()
2864 if (fitsRegularPattern<int>(Mid, 1, End, 0, 2)) in lowerVECTOR_SHUFFLE_PCKEV()
2866 else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size(), 2)) in lowerVECTOR_SHUFFLE_PCKEV()
2897 const auto &Mid = Indices.begin() + Indices.size() / 2; in lowerVECTOR_SHUFFLE_PCKOD() local
2900 if (fitsRegularPattern<int>(Begin, 1, Mid, 1, 2)) in lowerVECTOR_SHUFFLE_PCKOD()
2902 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size() + 1, 2)) in lowerVECTOR_SHUFFLE_PCKOD()
2907 if (fitsRegularPattern<int>(Mid, 1, End, 1, 2)) in lowerVECTOR_SHUFFLE_PCKOD()
2909 else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size() + 1, 2)) in lowerVECTOR_SHUFFLE_PCKOD()
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | Scalarizer.cpp | 774 Scatterer Mid = scatter(&BCI, V); in visitBitCastInst() local
776 Res[ResI++] = Mid[MidI]; in visitBitCastInst()
|
| /llvm-project-15.0.7/mlir/docs/Rationale/ |
| H A D | Rationale.md | 25 "Machine Learning IR" or "Mid Level IR", we prefer the first. This document only
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 13033 int Lo = Lane, Mid = Lane + NumHalfLaneElts, Hi = Lane + NumLaneElts; in lowerShuffleAsUNPCKAndPermute() local
13034 MatchLo &= isUndefOrInRange(M, Lo, Mid) || in lowerShuffleAsUNPCKAndPermute()
13035 isUndefOrInRange(M, NumElts + Lo, NumElts + Mid); in lowerShuffleAsUNPCKAndPermute()
13036 MatchHi &= isUndefOrInRange(M, Mid, Hi) || in lowerShuffleAsUNPCKAndPermute()
13037 isUndefOrInRange(M, NumElts + Mid, NumElts + Hi); in lowerShuffleAsUNPCKAndPermute()
48725 SDValue Mid = truncateVectorWithPACK(X86ISD::PACKUS, MVT::v16i16, USatVal, in combineTruncateWithSat() local
48727 assert(Mid && "Failed to pack!"); in combineTruncateWithSat()
48728 return DAG.getNode(X86ISD::VTRUNCUS, DL, VT, Mid); in combineTruncateWithSat()
48754 SDValue Mid = truncateVectorWithPACK(X86ISD::PACKSS, MidVT, USatVal, DL, in combineTruncateWithSat() local
48756 assert(Mid && "Failed to pack!"); in combineTruncateWithSat()
[all …]
|