| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVExpandAtomicPseudoInsts.cpp | 259 Register MaskReg, Register ScratchReg) { in insertMaskedMerge() argument
261 assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); in insertMaskedMerge()
262 assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); in insertMaskedMerge()
272 .addReg(MaskReg); in insertMaskedMerge()
287 Register MaskReg = MI.getOperand(4).getReg(); in doMaskedAtomicBinOpExpansion() local
427 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicMinMaxOp() local
443 .addReg(MaskReg); in expandAtomicMinMaxOp()
486 MaskReg, Scratch1Reg); in expandAtomicMinMaxOp()
568 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicCmpXchg() local
573 .addReg(MaskReg); in expandAtomicCmpXchg()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 101 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask() argument
107 MaskInst.addOperand(MCOperand::createReg(MaskReg)); in emitMask()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.h | 369 bool optimizePTestInstr(MachineInstr *PTest, unsigned MaskReg,
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| H A D | AArch64InstrInfo.cpp | 1293 MachineInstr *PTest, unsigned MaskReg, unsigned PredReg, in optimizePTestInstr() argument
1295 auto *Mask = MRI->getUniqueVRegDef(MaskReg); in optimizePTestInstr()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 211 Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy); in buildMaskLowPtrBits() local
212 buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits)); in buildMaskLowPtrBits()
213 return buildPtrMask(Res, Op0, MaskReg); in buildMaskLowPtrBits()
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| H A D | LegalizerHelper.cpp | 7222 Register MaskReg = MI.getOperand(1).getReg(); in lowerSelect() local
7226 LLT MaskTy = MRI.getType(MaskReg); in lowerSelect()
7233 Register MaskElt = MaskReg; in lowerSelect()
7248 MaskReg = ShufSplat.getReg(0); in lowerSelect()
7256 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg); in lowerSelect()
7257 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg); in lowerSelect()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 2549 Register MaskReg = I.getOperand(2).getReg(); in selectG_PTRMASK() local
2551 LLT MaskTy = MRI->getType(MaskReg); in selectG_PTRMASK()
2557 const RegisterBank *MaskRB = RBI.getRegBank(MaskReg, *MRI, TRI); in selectG_PTRMASK()
2564 APInt MaskOnes = KnownBits->getKnownOnes(MaskReg).zext(64); in selectG_PTRMASK()
2575 .addReg(MaskReg); in selectG_PTRMASK()
2591 !RBI.constrainGenericRegister(MaskReg, *MaskRC, *MRI)) in selectG_PTRMASK()
2600 .addReg(MaskReg); in selectG_PTRMASK()
2625 .addReg(MaskReg, 0, AMDGPU::sub0); in selectG_PTRMASK()
2639 .addReg(MaskReg, 0, AMDGPU::sub1); in selectG_PTRMASK()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11608 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary() local
11684 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitPartwordAtomicBinary()
11698 .addReg(MaskReg); in EmitPartwordAtomicBinary()
11699 BuildMI(BB, dl, TII->get(PPC::AND), Tmp3Reg).addReg(TmpReg).addReg(MaskReg); in EmitPartwordAtomicBinary()
11706 .addReg(MaskReg); in EmitPartwordAtomicBinary()
12618 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitInstrWithCustomInserter() local
12704 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitInstrWithCustomInserter()
12709 .addReg(MaskReg); in EmitInstrWithCustomInserter()
12712 .addReg(MaskReg); in EmitInstrWithCustomInserter()
12720 .addReg(MaskReg); in EmitInstrWithCustomInserter()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3048 Register MaskReg = I.getOperand(2).getReg(); in select() local
3049 Optional<int64_t> MaskVal = getIConstantVRegSExtVal(MaskReg, MRI); in select()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 4971 Register MaskReg = MIB.getReg(1); in expandPostRAPseudo() local
4979 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState) in expandPostRAPseudo()
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