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Searched refs:MaskLo (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1172 SDValue MaskLo, MaskHi; in SplitMask() local
1199 SDValue MaskLo, MaskHi; in SplitVecRes_BinOp() local
1233 SDValue MaskLo, MaskHi; in SplitVecRes_TernaryOp() local
1867 SDValue MaskLo, MaskHi; in SplitVecRes_VP_LOAD() local
1941 SDValue MaskLo, MaskHi; in SplitVecRes_MLOAD() local
2032 SDValue MaskLo, MaskHi; in SplitVecRes_Gather() local
2168 SDValue MaskLo, MaskHi; in SplitVecRes_UnaryOp() local
2903 SDValue MaskLo, MaskHi; in SplitVecOp_VP_REDUCE() local
3131 SDValue MaskLo, MaskHi; in SplitVecOp_VP_STORE() local
3209 SDValue MaskLo, MaskHi; in SplitVecOp_MSTORE() local
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H A DLegalizeIntegerTypes.cpp1375 SDValue MaskLo, MaskHi, EVLLo, EVLHi; in PromoteIntRes_TRUNCATE() local
1376 std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1)); in PromoteIntRes_TRUNCATE()
1379 EOp1 = DAG.getNode(ISD::VP_TRUNCATE, dl, HalfNVT, EOp1, MaskLo, EVLLo); in PromoteIntRes_TRUNCATE()
H A DTargetLowering.cpp2217 APInt MaskLo = DemandedBits.getLoBits(HalfBitWidth).trunc(HalfBitWidth); in SimplifyDemandedBits() local
2222 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownLo, TLO, Depth + 1)) in SimplifyDemandedBits()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp2659 Register MaskLo = B.buildConstant(S32, 0xffff).getReg(0); in applyMappingImpl() local
2660 MRI.setRegBank(MaskLo, *BankLo); in applyMappingImpl()
2668 ZextLo = B.buildAnd(S32, Lo, MaskLo).getReg(0); in applyMappingImpl()
H A DAMDGPUInstructionSelector.cpp2621 Register MaskLo = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() local
2624 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), MaskLo) in selectG_PTRMASK()
2628 .addReg(MaskLo); in selectG_PTRMASK()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp24645 static const int MaskLo[] = { 0, 0, 2, 2 }; in LowerVSETCC() local
24647 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo); in LowerVSETCC()