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Searched refs:Mag (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dvec-copysign-avx512.ll59 declare <4 x float> @llvm.copysign.v4f32(<4 x float> %Mag, <4 x float> %Sgn)
60 declare <8 x float> @llvm.copysign.v8f32(<8 x float> %Mag, <8 x float> %Sgn)
61 declare <16 x float> @llvm.copysign.v16f32(<16 x float> %Mag, <16 x float> %Sgn)
62 declare <2 x double> @llvm.copysign.v2f64(<2 x double> %Mag, <2 x double> %Sgn)
63 declare <4 x double> @llvm.copysign.v4f64(<4 x double> %Mag, <4 x double> %Sgn)
64 declare <8 x double> @llvm.copysign.v8f64(<8 x double> %Mag, <8 x double> %Sgn)
H A Dvec-copysign.ll155 declare <4 x float> @llvm.copysign.v4f32(<4 x float> %Mag, <4 x float> %Sgn)
156 declare <8 x float> @llvm.copysign.v8f32(<8 x float> %Mag, <8 x float> %Sgn)
157 declare <2 x double> @llvm.copysign.v2f64(<2 x double> %Mag, <2 x double> %Sgn)
158 declare <4 x double> @llvm.copysign.v4f64(<4 x double> %Mag, <4 x double> %Sgn)
H A Dcombine-fabs.ll139 declare float @llvm.copysign.f32(float %Mag, float %Sgn)
142 declare <4 x float> @llvm.copysign.v4f32(<4 x float> %Mag, <4 x float> %Sgn)
H A Dsse-fcopysign.ll269 declare dso_local float @llvm.copysign.f32(float %Mag, float %Sgn)
270 declare dso_local double @llvm.copysign.f64(double %Mag, double %Sgn)
271 declare dso_local x86_fp80 @llvm.copysign.f80(x86_fp80 %Mag, x86_fp80 %Sgn)
H A Dcombine-fcopysign.ll252 declare <4 x float> @llvm.copysign.v4f32(<4 x float> %Mag, <4 x float> %Sgn)
253 declare <4 x double> @llvm.copysign.v4f64(<4 x double> %Mag, <4 x double> %Sgn)
/llvm-project-15.0.7/llvm/test/CodeGen/VE/Scalar/
H A Dfcopysign.ll10 ;;; declare float @llvm.copysign.f32(float %Mag, float %Sgn)
11 ;;; declare double @llvm.copysign.f64(double %Mag, double %Sgn)
12 ;;; declare x86_fp80 @llvm.copysign.f80(x86_fp80 %Mag, x86_fp80 %Sgn)
13 ;;; declare fp128 @llvm.copysign.f128(fp128 %Mag, fp128 %Sgn)
14 ;;; declare ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128 %Mag, ppc_fp128 %Sgn)
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dfloat-intrinsics-double.ll123 declare double @llvm.copysign.f64(double %Mag, double %Sgn)
H A Dfloat-intrinsics-float.ll117 declare float @llvm.copysign.f32(float %Mag, float %Sgn)
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp1895 Value *Mag = II->getArgOperand(0), *Sign = II->getArgOperand(1); in visitCallInst() local
1899 Value *Fabs = Builder.CreateUnaryIntrinsic(Intrinsic::fabs, Mag, II); in visitCallInst()
1907 Value *Fabs = Builder.CreateUnaryIntrinsic(Intrinsic::fabs, Mag, II); in visitCallInst()
1920 if (match(Mag, m_FAbs(m_Value(X))) || match(Mag, m_FNeg(m_Value(X)))) in visitCallInst()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp1595 SDValue Mag = Node->getOperand(0); in ExpandFCOPYSIGN() local
1608 EVT FloatVT = Mag.getValueType(); in ExpandFCOPYSIGN()
1611 SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag); in ExpandFCOPYSIGN()
1620 getSignAsIntValue(MagAsInt, DL, Mag); in ExpandFCOPYSIGN()
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Df128-arith.ll258 declare fp128 @llvm.copysign.f128(fp128 %Mag, fp128 %Sgn)
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp6098 SDValue Mag = Op.getOperand(0); in lowerFixedLengthVectorFCOPYSIGNToRVV() local
6100 assert(Mag.getValueType() == Sign.getValueType() && in lowerFixedLengthVectorFCOPYSIGNToRVV()
6104 Mag = convertToScalableVector(ContainerVT, Mag, DAG, Subtarget); in lowerFixedLengthVectorFCOPYSIGNToRVV()
6111 DAG.getNode(RISCVISD::FCOPYSIGN_VL, DL, ContainerVT, Mag, Sign, Mask, VL); in lowerFixedLengthVectorFCOPYSIGNToRVV()
/llvm-project-15.0.7/llvm/docs/
H A DLangRef.rst14647 declare float @llvm.copysign.f32(float %Mag, float %Sgn)
14648 declare double @llvm.copysign.f64(double %Mag, double %Sgn)
14649 declare x86_fp80 @llvm.copysign.f80(x86_fp80 %Mag, x86_fp80 %Sgn)
14650 declare fp128 @llvm.copysign.f128(fp128 %Mag, fp128 %Sgn)
14651 declare ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128 %Mag, ppc_fp128 %Sgn)
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp23248 SDValue Mag = Op.getOperand(0); in LowerFCOPYSIGN() local
23299 if (ConstantFPSDNode *Op0CN = isConstOrConstSplatFP(Mag)) { in LowerFCOPYSIGN()
23306 Mag = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Mag); in LowerFCOPYSIGN()
23307 MagBits = DAG.getNode(X86ISD::FAND, dl, LogicVT, Mag, MagMask); in LowerFCOPYSIGN()