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Searched refs:MTC1 (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dfloat_constants.mir21 ; FP32: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 [[ORi]]
27 ; FP64: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 [[ORi]]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp122 Opc = Mips::MTC1; in copyPhysReg()
448 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); in expandPostRAPseudo()
452 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false); in expandPostRAPseudo()
459 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true); in expandPostRAPseudo()
829 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); in expandBuildPairF64()
H A DMipsInstructionSelector.cpp603 MachineInstrBuilder MTC1 = in select() local
604 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); in select()
605 if (!MTC1.constrainAllUses(TII, TRI, RBI)) in select()
H A DMipsAsmPrinter.cpp882 if (Opcode == Mips::MTC1) { in EmitInstrRegReg()
922 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams()
H A DMipsInstrFPU.td564 def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
937 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>, ISA_MIPS1;
938 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>, ISA_MIPS1;
H A DMipsInstrInfo.cpp633 case Mips::MTC1: in HasFPUDelaySlot()
H A DMipsScheduleP5600.td564 def : InstRW<[P5600WriteMoveGPRToFPU], (instrs CTC1, MTC1, MTC1_D64, MTHC1_D32,
H A DMipsFastISel.cpp392 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
H A DMipsScheduleGeneric.td872 MFHC1_D64, MTC1, MTC1_D64,
H A DMipsSEISelLowering.cpp3767 : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1); in emitFPEXTEND_PSEUDO()
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dselect-dbl.ll102 ; MM32R3: mtc1 $7, $f2 # <MCInst #{{.*}} MTC1
/llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp3400 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadSingleImmToFPR()
3530 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
3533 TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3534 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()