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Searched refs:MRMSrcReg (Results 1 – 23 of 23) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrExtension.td39 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
47 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
55 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
65 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
73 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
81 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
94 def MOVSX16rr16: I<0xBF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
97 def MOVZX16rr16: I<0xB7, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
114 def MOVZX32rr8_NOREX : I<0xB6, MRMSrcReg,
124 def MOVSX32rr8_NOREX : I<0xBE, MRMSrcReg,
[all …]
H A DX86InstrMMX.td37 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
55 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
93 def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
110 def rri : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
137 def rr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
237 def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
242 def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst),
252 def MMX_MOVFR642Qrr: MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
476 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
516 def MMX_PEXTRWrr: MMXIi8<0xC5, MRMSrcReg,
[all …]
H A DX86InstrKL.td20 def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
27 def ENCODEKEY128 : I<0xFA, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
33 def ENCODEKEY256 : I<0xFB, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
H A DX86InstrSSE.td1836 def rr : SIi8<0xC2, MRMSrcReg,
1958 def rri : PIi8<0xC2, MRMSrcReg,
2102 def rr : PI<opc, MRMSrcReg,
3730 def ri : Ii8<0x70, MRMSrcReg,
3765 def rr : PDI<opc, MRMSrcReg,
3790 def rr : SS48I<opc, MRMSrcReg,
3866 def rr : PDI<opc, MRMSrcReg,
3969 def rr : Ii8<0xC4, MRMSrcReg,
3992 def VPEXTRWrr : Ii8<0xC5, MRMSrcReg,
4532 def rr : I<0xD0, MRMSrcReg,
[all …]
H A DX86InstrXOP.td14 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
45 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
56 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
67 def Yrr : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
118 def rr_REV : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
142 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
171 def rr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst),
248 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
284 def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst),
331 def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs RC:$dst),
[all …]
H A DX86InstrSystem.td34 def UD1Wr : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
36 def UD1Lr : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
38 def UD1Qr : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
133 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
136 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
152 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
155 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
198 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
200 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
202 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
[all …]
H A DX86InstrFMA.td39 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
60 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
80 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
181 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst),
202 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst),
222 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst),
272 def r_Int : FMA3S_Int<opc, MRMSrcReg, (outs RC:$dst),
422 def rr_REV : FMA4S<opc, MRMSrcReg, (outs RC:$dst),
457 def rr_Int_REV : FMA4S_Int<opc, MRMSrcReg, (outs VR128:$dst),
526 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
[all …]
H A DX86InstrVMX.td67 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
70 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
H A DX86Instr3DNow.td32 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
45 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
H A DX86InstrAVX512.td1361 defm rr : AVX512_maskable_custom<opc, MRMSrcReg,
2129 def rr : AVX512Ii8<0xC2, MRMSrcReg,
2178 def rr : AVX512BI<opc, MRMSrcReg,
2188 def rrk : AVX512BI<opc, MRMSrcReg,
2316 def rri : AVX512AIi8<opc, MRMSrcReg,
2335 def rrik : AVX512AIi8<opc, MRMSrcReg,
5569 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
5616 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
5702 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
11724 def rr : AVX512BI<opc, MRMSrcReg,
[all …]
H A DX86InstrArithmetic.td164 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
201 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
219 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
676 : ITy<opcode, MRMSrcReg, typeinfo,
693 : ITy<opcode, MRMSrcReg, typeinfo, (outs),
1464 def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1498 def rr : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src),
1538 def ADCX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst),
1541 def ADCX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst),
1545 def ADOX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst),
[all …]
H A DX86InstrInfo.td1491 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1499 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1507 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1516 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1524 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1532 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1782 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
2127 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst1, GR8:$dst2),
2130 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst1, GR16:$dst2),
2134 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst1, GR32:$dst2),
[all …]
H A DX86InstrFormats.td45 def MRMSrcReg : Format<41>;
H A DX86MCInstLower.cpp978 (TSFlags & X86II::FormMask) == X86II::MRMSrcReg && in Lower()
H A DX86InstrShiftRotate.td875 def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, u8imm:$src2),
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DX86RecognizableInstr.h121 MRMSrcReg = 41, enumerator
H A DX86RecognizableInstr.cpp135 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); in RecognizableInstrBase()
572 case X86Local::MRMSrcReg: in emitInstructionSpecifier()
802 case X86Local::MRMSrcReg: in emitDecodePath()
H A DX86FoldTablesEmitter.cpp377 (MemForm == X86Local::MRMSrcMem && RegForm == X86Local::MRMSrcReg) || in areOppositeForms()
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86BaseInfo.h695 MRMSrcReg = 41, enumerator
1132 case X86II::MRMSrcReg: in getMemoryOperandNo()
H A DX86MCCodeEmitter.cpp932 case X86II::MRMSrcReg: { in emitVEXOpcodePrefix()
1166 case X86II::MRMSrcReg: in emitREXPrefix()
1449 case X86II::MRMSrcReg: { in encodeInstruction()
/llvm-project-15.0.7/llvm/test/TableGen/
H A DTargetInstrInfo.td50 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/X86/
H A DTarget.cpp71 case X86II::MRMSrcReg: in isInvalidMemoryInstr()
/llvm-project-15.0.7/llvm/docs/
H A DWritingAnLLVMBackend.rst1864 case X86II::MRMSrcReg: // for instructions that use the Mod/RM byte