| /llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/ |
| H A D | TargetTest.cpp | 186 EXPECT_THAT(setRegTo(X86::MM0, APInt(64, 0x1111222233334444ULL)), in TEST_F()
190 IsMovValueFromStack(X86::MMX_MOVQ64rm, X86::MM0), in TEST_F()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86Instr3DNow.td | 77 Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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| H A D | X86CallingConv.td | 258 // MMX vector types are always returned in MM0. If the target doesn't have
259 // MM0, it doesn't support these vector types.
260 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
857 CCAssignToReg<[MM0, MM1, MM2]>>>,
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| H A D | X86InstrMMX.td | 152 Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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| H A D | X86RegisterInfo.td | 192 def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>;
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| H A D | X86InstrCompiler.td | 459 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
479 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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| /llvm-project-15.0.7/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86DisassemblerDecoder.h | 206 ENTRY(MM0) \
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| /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 224 {codeview::RegisterId::MM0, X86::MM0}, in initLLVMToSEHAndCVRegMapping()
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| H A D | X86InstComments.cpp | 243 if (X86::MM0 <= RegNo && RegNo <= X86::MM7) in getVectorRegSize()
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| /llvm-project-15.0.7/llvm/include/llvm/DebugInfo/CodeView/ |
| H A D | CodeViewRegisters.def | 143 CV_REGISTER(MM0, 146)
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| /llvm-project-15.0.7/llvm/docs/TableGen/ |
| H A D | index.rst | 69 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R10, R10B, R10D, R10W, R11, R11B, R11D,
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| H A D | ProgRef.rst | 866 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, XMM0, XMM1, XMM2,
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| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 5739 auto *MM0 = dyn_cast<IntrinsicInst>(Op0); in foldMinMaxSharedOp() local
5740 if (!MM0) in foldMinMaxSharedOp()
5742 Intrinsic::ID IID0 = MM0->getIntrinsicID(); in foldMinMaxSharedOp()
5748 return MM0; in foldMinMaxSharedOp()
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| /llvm-project-15.0.7/llvm/docs/ |
| H A D | CodeGenerator.rst | 1278 ``EAX`` is denoted by 43, and the MMX register ``MM0`` is mapped to 65.
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