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Searched refs:MIs (Results 1 – 25 of 31) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DInstructionSelectorImpl.h65 const uint16_t Flags = State.MIs[0]->getFlags(); in executeMatchTable()
130 if ((size_t)NewInsnID < State.MIs.size()) in executeMatchTable()
131 State.MIs[NewInsnID] = NewMI; in executeMatchTable()
135 State.MIs.push_back(NewMI); in executeMatchTable()
347 const MachineInstr *MI = State.MIs[InsnID]; in executeMatchTable()
389 const MachineInstr *MI = State.MIs[InsnID]; in executeMatchTable()
813 if (!isObviouslySafeToFold(*State.MIs[InsnID], *State.MIs[0])) { in executeMatchTable()
867 OutMIs[NewInsnID] = BuildMI(*State.MIs[0]->getParent(), State.MIs[0], in executeMatchTable()
1059 OutMIs[InsnID], *State.MIs[OldInsnID], in executeMatchTable()
1132 assert(State.MIs[InsnID] && in executeMatchTable()
[all …]
H A DInstructionSelector.h477 RecordedMIVector MIs; member
/llvm-project-15.0.7/llvm/test/TableGen/
H A DGlobalISelEmitterCustomPredicate.td75 // CHECK-NEXT: // MIs[0] dst
78 // CHECK-NEXT: // MIs[0] src2
89 // CHECK-NEXT: // MIs[1] src0
93 // CHECK-NEXT: // MIs[1] src1
105 // CHECK-NEXT: // MIs[0] dst
115 // CHECK-NEXT: // MIs[1] src0
119 // CHECK-NEXT: // MIs[1] src1
123 // CHECK-NEXT: // MIs[0] src2
152 // CHECK-NEXT: // MIs[0] dst
162 // CHECK-NEXT: // MIs[1] src0
[all …]
H A DGlobalISelEmitter.td254 // R19N-NEXT: // MIs[0] dst
257 // R19N-NEXT: // MIs[0] src1
271 // R19N-NEXT: // MIs[1] src3
276 // R19N-NEXT: // MIs[1] src4
348 // R21N-NEXT: // MIs[0] dst
351 // R21N-NEXT: // MIs[0] src1
354 // R21N-NEXT: // MIs[0] src2
404 // R20N-NEXT: // MIs[0] dst
469 // R00N-NEXT: // MIs[0] dst
551 // R01N-NEXT: // MIs[0] dst
[all …]
H A DGlobalISelEmitter-immAllZeroOne.td26 // GISEL-NOOPT: // MIs[0] Operand 2
28 // GISEL-NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
31 // GISEL-NOOPT-NEXT: // MIs[1] Operand 0
41 // GISEL-NOOPT: // MIs[0] Operand 2
43 // GISEL-NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46 // GISEL-NOOPT-NEXT: // MIs[1] Operand 0
H A Dgisel-physreg-input.td30 // GISEL-NEXT: // MIs[0] dst
33 // GISEL-NEXT: // MIs[0] src0
36 // GISEL-NEXT: // MIs[0] Operand 2
58 // GISEL-NEXT: // MIs[0] dst
61 // GISEL-NEXT: // MIs[0] SPECIAL
64 // GISEL-NEXT: // MIs[0] Operand 2
H A DGlobalISelEmitter-immarg-literal-pattern.td27 // GISEL-NEXT: // MIs[0] Operand 1
36 // GISEL-NEXT: // MIs[0] Operand 1
47 // GISEL-NEXT: // MIs[0] Operand 2
56 // GISEL-NEXT: // MIs[0] Operand 2
H A DGlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td18 // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22 // CHECK-NEXT: // MIs[1] Operand 1
26 // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
46 // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50 // CHECK-NEXT: // MIs[1] Operand 1
54 // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
H A DContextlessPredicates.td29 // CHECK_NOPT-NEXT: // MIs[0] dst
32 // CHECK_NOPT-NEXT: // MIs[0] ptr
35 // CHECK_NOPT-NEXT: // MIs[0] val
60 // CHECK_OPT-NEXT: // MIs[0] ptr
H A Dimmarg-predicated.td11 // GISEL-NEXT: // MIs[0] Operand 0
13 // GISEL-NEXT: // MIs[0] src
H A DGlobalISelEmitter-atomic_store.td14 // GISEL-NEXT: // MIs[0] ptr
16 // GISEL-NEXT: // MIs[0] val
H A Dimmarg.td12 // GISEL-NEXT: // MIs[0] Operand 0
14 // GISEL-NEXT: // MIs[0] src
H A DGlobalISelEmitter-zero-reg.td27 // CHECK-NEXT: // MIs[0] dst
30 // CHECK-NEXT: // MIs[0] src
H A DGlobalISelEmitterMatchTableOptimizer.td16 // CHECK-NEXT: // MIs[0] src
26 // CHECK-NEXT: // MIs[0] src
55 // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
H A DGlobalISelEmitter-nested-subregs.td35 // CHECK-NEXT: // MIs[0] dst
38 // CHECK-NEXT: // MIs[0] src
H A DGlobalISelEmitterRegSequence.td35 // CHECK-NEXT: // MIs[0] dst
38 // CHECK-NEXT: // MIs[0] src
H A DGlobalISelEmitterOverloadedPtr.td17 // CHECK-NEXT: // MIs[0] src
H A DHasNoUse.td24 // GISEL-NEXT: // MIs[0] src0
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVMakeCompressible.cpp225 SmallVectorImpl<MachineInstr *> &MIs) { in analyzeCompressibleUses() argument
247 MIs.push_back(&MI); in analyzeCompressibleUses()
264 if (MIs.size() < 2 || (RegImm.Imm != 0 && MIs.size() < 3)) in analyzeCompressibleUses()
350 SmallVector<MachineInstr *, 8> MIs; in runOnMachineFunction() local
351 Register NewReg = analyzeCompressibleUses(MI, RegImm, MIs); in runOnMachineFunction()
380 for (MachineInstr *UpdateMI : MIs) in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp236 std::vector<MachineInstr *> &MIs = It.second; in RemoveMI() local
237 MIs.erase(llvm::find(MIs, MI), MIs.end()); in RemoveMI()
240 std::vector<MachineInstr *> &MIs = It.second; in RemoveMI() local
241 MIs.erase(llvm::find(MIs, MI), MIs.end()); in RemoveMI()
298 std::vector<MachineInstr *> &MIs = in tryMergeUsingFreeSlot() local
300 CompatibleRSI = PreviousRegSeq[MIs.back()]; in tryMergeUsingFreeSlot()
H A DR600InstrInfo.h142 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DVirtRegMap.cpp449 SmallVector<MachineInstr *, 2> MIs({&MI}); in expandCopyBundle() local
458 MIs.push_back(&*I); in expandCopyBundle()
460 MachineInstr *FirstMI = MIs.back(); in expandCopyBundle()
476 for (int E = MIs.size(), PrevE = E; E > 1; PrevE = E) { in expandCopyBundle()
478 if (!anyRegsAlias(MIs[I], makeArrayRef(MIs).take_front(E), TRI)) { in expandCopyBundle()
480 std::swap(MIs[I], MIs[E - 1]); in expandCopyBundle()
491 for (MachineInstr *BundledMI : llvm::reverse(MIs)) { in expandCopyBundle()
H A DMachineInstr.cpp398 ArrayRef<const MachineInstr *> MIs) { in cloneMergedMemRefs() argument
400 if (MIs.empty()) { in cloneMergedMemRefs()
404 if (MIs.size() == 1) { in cloneMergedMemRefs()
405 cloneMemRefs(MF, *MIs[0]); in cloneMergedMemRefs()
411 if (MIs[0]->memoperands_empty()) { in cloneMergedMemRefs()
419 assert(&MF == MIs[0]->getMF() && in cloneMergedMemRefs()
421 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end()); in cloneMergedMemRefs()
423 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) { in cloneMergedMemRefs()
430 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands())) in cloneMergedMemRefs()
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dsetmemrefs.ll4 ; memrefs of the resulting load MIs correctly, so that they are packetized
H A Dtrivialmemaliascheck.ll6 ; surface. do not have only one mem operand. However, the backend knows MIs and

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