Searched refs:MIOpc (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64CondBrTuning.cpp | 146 unsigned MIOpc = MI.getOpcode(); in tryToTuneBranch() local 179 switch (MIOpc) { in tryToTuneBranch() 188 if ((MIOpc == AArch64::TBZW || MIOpc == AArch64::TBNZW) && in tryToTuneBranch() 235 switch (MIOpc) { in tryToTuneBranch() 244 if ((MIOpc == AArch64::TBZX || MIOpc == AArch64::TBNZX) && in tryToTuneBranch()
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| H A D | AArch64InstrInfo.cpp | 1721 unsigned MIOpc = MI.getOpcode(); in canCmpInstrBeRemoved() local 1722 if (MIOpc == AArch64::CSINCWr) { in canCmpInstrBeRemoved() 1726 } else if (MIOpc == AArch64::CSINCXr) { in canCmpInstrBeRemoved()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 602 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstr &MI,
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| H A D | X86InstrInfo.cpp | 1184 switch (MIOpc) { in convertToThreeAddressWithLEA() 1340 unsigned MIOpc = MI.getOpcode(); in convertToThreeAddress() local 1341 switch (MIOpc) { in convertToThreeAddress() 1398 return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp); in convertToThreeAddress() 1403 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r : in convertToThreeAddress() 1424 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r in convertToThreeAddress() 1449 return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp); in convertToThreeAddress() 1456 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) in convertToThreeAddress() 1498 return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp); in convertToThreeAddress() 1617 switch (MIOpc) { in convertToThreeAddress() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 253 static ISD::NodeType extOpcodeToISDExtOpcode(unsigned MIOpc) { in extOpcodeToISDExtOpcode() argument 254 switch (MIOpc) { in extOpcodeToISDExtOpcode()
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