Searched refs:MI3 (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/unittests/CodeGen/ |
| H A D | MachineInstrTest.cpp | 84 auto MI3 = MF->CreateMachineInstr(MCID, DebugLoc()); in TEST() local
85 MI3->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); in TEST()
86 MI3->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ true)); in TEST()
93 ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::CheckDefs)); in TEST()
94 ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::CheckDefs)); in TEST()
96 ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::IgnoreVRegDefs)); in TEST()
97 ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::IgnoreVRegDefs)); in TEST()
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRExpandPseudoInsts.cpp | 1524 auto MI3 = in expandLSLW4Rd() local
1530 MI3->getOperand(3).setIsDead(); in expandLSLW4Rd()
1722 auto MI3 = in expandLSRW4Rd() local
1728 MI3->getOperand(3).setIsDead(); in expandLSRW4Rd()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 814 class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3>
816 (MI1 (MI2 $Rs, $Rt), (MI3 $Rs, $Rt))>;
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