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Searched refs:MFENCE (Results 1 – 13 of 13) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/MCA/
H A DX86CustomBehaviour.cpp26 case X86::MFENCE: in setMemBarriers()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86SpeculativeLoadHardening.cpp387 if (MI.getOpcode() == X86::MFENCE) in hasVulnerableLoad()
1317 if (MI.getOpcode() == X86::MFENCE) in tracePredStateThroughBlocksAndHarden()
H A DX86LoadValueInjectionLoadHardening.cpp771 if (!MI.mayLoadOrStore() || MI.getOpcode() == X86::MFENCE || in instrUsesRegToAccessMemory()
H A DX86ISelLowering.h664 MFENCE, enumerator
H A DX86SchedSkylakeClient.td836 def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
H A DX86SchedBroadwell.td715 MFENCE,
H A DX86SchedHaswell.td1131 MFENCE,
H A DX86SchedSkylakeServer.td905 def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
H A DX86SchedIceLake.td923 def: InstRW<[ICXWriteResGroup43], (instrs MFENCE)>;
H A DX86InstrSSE.td3236 def MFENCE : I<0xAE, MRM6X, (outs), (ins), "mfence", [(int_x86_sse2_mfence)]>,
3240 def : Pat<(X86MFence), (MFENCE)>;
H A DX86InstrInfo.td136 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
H A DX86ISelLowering.cpp31148 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); in LowerATOMIC_FENCE()
33655 NODE_NAME_CASE(MFENCE) in getTargetNodeName()
/llvm-project-15.0.7/llvm/docs/
H A DAtomics.rst438 fences generate an ``MFENCE``, other fences do not cause any code to be