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Searched refs:MCRegister (Results 1 – 25 of 188) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCRegisterInfo.h78 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains()
461 MCRegister getSubReg(MCRegister Reg, unsigned Idx) const;
465 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
471 unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const;
560 bool isSubRegister(MCRegister RegA, MCRegister RegB) const { in isSubRegister()
565 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const;
568 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSubRegisterEq()
574 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperRegisterEq()
580 bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperOrSubRegisterEq()
585 bool regsOverlap(MCRegister RegA, MCRegister RegB) const;
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H A DMCRegister.h24 class MCRegister {
25 friend hash_code hash_value(const MCRegister &);
29 constexpr MCRegister(unsigned Val = 0): Reg(Val) {} in Reg()
67 static MCRegister from(unsigned Val) { in from()
69 return MCRegister(Val); in from()
79 bool operator==(const MCRegister &Other) const { return Reg == Other.Reg; }
80 bool operator!=(const MCRegister &Other) const { return Reg != Other.Reg; }
96 template<> struct DenseMapInfo<MCRegister> {
103 static unsigned getHashValue(const MCRegister &Val) {
106 static bool isEqual(const MCRegister &LHS, const MCRegister &RHS) {
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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRegister.h24 constexpr Register(MCRegister Val): Reg(Val) {} in Register()
45 return MCRegister::isStackSlot(Reg); in isStackSlot()
66 return MCRegister::isPhysicalRegister(Reg); in isPhysicalRegister()
72 return Reg & MCRegister::VirtualRegFlag; in isVirtualRegister()
79 return Reg & ~MCRegister::VirtualRegFlag; in virtReg2Index()
86 return Index | MCRegister::VirtualRegFlag; in index2VirtReg()
113 operator MCRegister() const { in MCRegister() function
114 return MCRegister(Reg); in MCRegister()
120 MCRegister asMCReg() const { in asMCReg()
121 assert(Reg == MCRegister::NoRegister || in asMCReg()
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H A DReachingDefAnalysis.h142 int getReachingDef(MachineInstr *MI, MCRegister PhysReg) const;
146 MCRegister PhysReg) const;
155 MCRegister PhysReg) const;
160 MCRegister PhysReg) const;
176 bool isRegUsedAfter(MachineInstr *MI, MCRegister PhysReg) const;
183 int getClearance(MachineInstr *MI, MCRegister PhysReg) const;
187 void getReachingLocalUses(MachineInstr *MI, MCRegister PhysReg,
194 void getLiveOuts(MachineBasicBlock *MBB, MCRegister PhysReg,
200 bool getLiveInUses(MachineBasicBlock *MBB, MCRegister PhysReg,
239 bool isSafeToDefRegAt(MachineInstr *MI, MCRegister PhysReg,
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H A DLiveRegMatrix.h108 MCRegister PhysReg);
115 bool checkInterference(SlotIndex Start, SlotIndex End, MCRegister PhysReg);
120 void assign(const LiveInterval &VirtReg, MCRegister PhysReg);
128 bool isPhysRegUsed(MCRegister PhysReg) const;
141 MCRegister PhysReg = MCRegister::NoRegister);
147 MCRegister PhysReg);
153 LiveIntervalUnion::Query &query(const LiveRange &LR, MCRegister RegUnit);
H A DTargetRegisterInfo.h88 MCRegister getRegister(unsigned i) const { in getRegister()
362 bool isInAllocatableClass(MCRegister RegNo) const { in isInAllocatableClass()
428 bool hasRegUnit(MCRegister Reg, Register RegUnit) const { in hasRegUnit()
529 MCRegister PhysReg) const { in isAsmClobberable()
553 virtual bool isCallerPreservedPhysReg(MCRegister PhysReg, in isCallerPreservedPhysReg()
560 virtual bool isCalleeSavedPhysReg(MCRegister PhysReg,
565 MCRegister PhysReg) const { in isArgumentRegister()
571 MCRegister PhysReg) const { in isFixedRegister()
588 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
1022 virtual StringRef getRegAsmName(MCRegister Reg) const { in getRegAsmName()
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H A DMachineRegisterInfo.h144 std::vector<std::pair<MCRegister, Register>> LiveIns;
238 MCRegister Reg) const;
243 void disableCalleeSavedRegister(MCRegister Reg);
628 bool isConstantPhysReg(MCRegister PhysReg) const;
834 void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg, in updateDbgUsersToReg()
907 bool canReserveReg(MCRegister PhysReg) const { in canReserveReg()
925 bool isReserved(MCRegister PhysReg) const { in isReserved()
943 bool isAllocatable(MCRegister PhysReg) const { in isAllocatable()
966 ArrayRef<std::pair<MCRegister, Register>> liveins() const { in liveins()
974 MCRegister getLiveInPhysReg(Register VReg) const;
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H A DCallingConvLower.h275 bool isAllocated(MCRegister Reg) const { in isAllocated()
326 bool IsShadowAllocatedReg(MCRegister Reg) const;
349 MCRegister AllocateReg(MCPhysReg Reg) { in AllocateReg()
351 return MCRegister(); in AllocateReg()
357 MCRegister AllocateReg(MCPhysReg Reg, MCPhysReg ShadowReg) { in AllocateReg()
359 return MCRegister(); in AllocateReg()
371 return MCRegister(); // Didn't find the reg. in AllocateReg()
409 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
412 return MCRegister(); // Didn't find the reg. in AllocateReg()
415 MCRegister Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; in AllocateReg()
H A DRegisterClassInfo.h119 MCRegister getLastCalleeSavedAlias(MCRegister PhysReg) const { in getLastCalleeSavedAlias()
122 return MCRegister::NoRegister; in getLastCalleeSavedAlias()
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCRegisterInfo.cpp23 MCRegister
24 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
32 MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const { in getSubReg()
44 unsigned MCRegisterInfo::getSubRegIndex(MCRegister Reg, in getSubRegIndex()
45 MCRegister SubReg) const { in getSubRegIndex()
68 int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const { in getDwarfRegNum()
109 int MCRegisterInfo::getSEHRegNum(MCRegister RegNum) const { in getSEHRegNum()
110 const DenseMap<MCRegister, int>::const_iterator I = L2SEHRegs.find(RegNum); in getSEHRegNum()
115 int MCRegisterInfo::getCodeViewRegNum(MCRegister RegNum) const { in getCodeViewRegNum()
118 const DenseMap<MCRegister, int>::const_iterator I = L2CVRegs.find(RegNum); in getCodeViewRegNum()
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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRegAllocGreedy.h216 MCRegister PhysReg;
228 void reset(InterferenceCache &Cache, MCRegister Reg) { in reset()
287 MCRegister selectOrSplit(const LiveInterval &,
307 MCRegister selectOrSplitImpl(const LiveInterval &,
326 void calcGapWeights(MCRegister, SmallVectorImpl<float> &);
327 void evictInterference(const LiveInterval &, MCRegister,
329 bool mayRecolorAllInterferences(MCRegister PhysReg,
334 MCRegister tryAssign(const LiveInterval &, AllocationOrder &,
336 MCRegister tryEvict(const LiveInterval &, AllocationOrder &,
351 MCRegister tryAssignCSRFirstTime(const LiveInterval &VirtReg,
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H A DMachineCopyPropagation.cpp107 SmallVector<MCRegister, 4> DefRegs;
111 DenseMap<MCRegister, CopyInfo> Copies;
118 for (MCRegister Reg : Regs) { in markRegsUnavailable()
134 SmallSet<MCRegister, 8> RegsToInvalidate; in invalidateRegister()
327 bool eraseIfRedundant(MachineInstr &Copy, MCRegister Src, MCRegister Def);
402 MCRegister Src, MCRegister Def) { in eraseIfRedundant()
667 MCRegister Def = RegDef.asMCReg(); in ForwardCopyPropagateBlock()
668 MCRegister Src = RegSrc.asMCReg(); in ForwardCopyPropagateBlock()
807 for (MCRegister Reg : Defs) in ForwardCopyPropagateBlock()
934 MCRegister Def = DefReg.asMCReg(); in BackwardCopyPropagateBlock()
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H A DLiveRegMatrix.cpp81 const LiveInterval &VRegInterval, MCRegister PhysReg, in foreachUnit()
104 void LiveRegMatrix::assign(const LiveInterval &VirtReg, MCRegister PhysReg) { in assign()
138 bool LiveRegMatrix::isPhysRegUsed(MCRegister PhysReg) const { in isPhysRegUsed()
147 MCRegister PhysReg) { in checkRegMaskInterference()
165 MCRegister PhysReg) { in checkRegUnitInterference()
179 MCRegister RegUnit) { in query()
187 MCRegister PhysReg) { in checkInterference()
201 [&](MCRegister Unit, const LiveRange &LR) { in checkInterference()
211 MCRegister PhysReg) { in checkInterference()
247 return MCRegister::NoRegister; in getOneVReg()
H A DRegAllocEvictionAdvisor.h108 virtual MCRegister tryFindEvictionCandidate(
115 canEvictHintInterference(const LiveInterval &VirtReg, MCRegister PhysReg,
120 bool isUnusedCalleeSavedReg(MCRegister PhysReg) const;
136 bool canAllocatePhysReg(unsigned CostPerUseLimit, MCRegister PhysReg) const;
209 MCRegister tryFindEvictionCandidate(const LiveInterval &,
212 bool canEvictHintInterference(const LiveInterval &, MCRegister,
214 bool canEvictInterferenceBasedOnCost(const LiveInterval &, MCRegister, bool,
H A DReachingDefAnalysis.cpp33 static bool isValidRegUseOf(const MachineOperand &MO, MCRegister PhysReg, in isValidRegUseOf()
44 static bool isValidRegDefOf(const MachineOperand &MO, MCRegister PhysReg, in isValidRegDefOf()
264 MCRegister PhysReg) const { in getReachingDef()
285 MCRegister PhysReg) const { in getReachingLocalMIDef()
321 MCRegister PhysReg) const { in getClearance()
327 MCRegister PhysReg) const { in hasLocalDefBefore()
332 MCRegister PhysReg, in getReachingLocalUses()
357 MCRegister PhysReg, in getLiveInUses()
401 MCRegister PhysReg, in getGlobalReachingDefs()
471 MCRegister PhysReg) const { in isRegUsedAfter()
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H A DInterferenceCache.h47 MCRegister PhysReg = 0;
105 PhysReg = MCRegister::NoRegister; in clear()
111 MCRegister getPhysReg() const { return PhysReg; } in getPhysReg()
123 void reset(MCRegister physReg, LiveIntervalUnion *LIUArray,
155 Entry *get(MCRegister PhysReg);
208 void setPhysReg(InterferenceCache &Cache, MCRegister PhysReg) { in setPhysReg()
H A DMachineRegisterInfo.cpp433 for (const std::pair<MCRegister, Register> &LI : liveins()) in isLiveIn()
441 MCRegister MachineRegisterInfo::getLiveInPhysReg(Register VReg) const { in getLiveInPhysReg()
442 for (const std::pair<MCRegister, Register> &LI : liveins()) in getLiveInPhysReg()
445 return MCRegister(); in getLiveInPhysReg()
451 for (const std::pair<MCRegister, Register> &LI : liveins()) in getLiveInVirtReg()
566 bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg, in isPhysRegModified()
581 bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg, in isPhysRegUsed()
594 void MachineRegisterInfo::disableCalleeSavedRegister(MCRegister Reg) { in disableCalleeSavedRegister()
642 MCRegister Reg = *Super; in isReservedRegUnit()
655 MCRegister Reg) const { in isArgumentRegister()
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H A DRegAllocBasic.cpp99 MCRegister selectOrSplit(const LiveInterval &VirtReg,
118 bool spillInterferences(const LiveInterval &VirtReg, MCRegister PhysReg,
209 MCRegister PhysReg, in spillInterferences()
259 MCRegister RABasic::selectOrSplit(const LiveInterval &VirtReg, in selectOrSplit()
262 SmallVector<MCRegister, 8> PhysRegSpillCands; in selectOrSplit()
267 for (MCRegister PhysReg : Order) { in selectOrSplit()
287 for (MCRegister &PhysReg : PhysRegSpillCands) { in selectOrSplit()
H A DRegAllocEvictionAdvisor.cpp168 const LiveInterval &VirtReg, MCRegister PhysReg, in canEvictHintInterference()
186 const LiveInterval &VirtReg, MCRegister PhysReg, bool IsHint, in canEvictInterferenceBasedOnCost()
275 MCRegister DefaultEvictionAdvisor::tryFindEvictionCandidate( in tryFindEvictionCandidate()
281 MCRegister BestPhys; in tryFindEvictionCandidate()
284 return MCRegister::NoRegister; in tryFindEvictionCandidate()
296 MCRegister PhysReg = *I; in tryFindEvictionCandidate()
H A DRegAllocGreedy.cpp368 MCRegister PhysReg; in tryAssign()
387 MCRegister PhysHint = Hint.asMCReg(); in tryAssign()
421 MCRegister PhysReg; in canReassign()
1012 return MCRegister::NoRegister; in tryRegionSplit()
1036 return MCRegister::NoRegister; in tryRegionSplit()
1802 for (MCRegister PhysReg : Order) { in tryLastChanceRecoloring()
1888 MCRegister PhysReg; in tryLastChanceRecoloring()
1897 MCRegister PhysReg; in tryLastChanceRecoloring()
1961 MCRegister Reg = in selectOrSplit()
2066 MCRegister OtherPhysReg = in collectHintInfo()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h49 void reserveRegisterTuples(BitVector &, MCRegister Reg) const;
79 MCRegister PhysReg) const override;
162 StringRef getRegAsmName(MCRegister Reg) const override;
165 unsigned getHWRegIndex(MCRegister Reg) const { in getHWRegIndex()
184 const TargetRegisterClass *getPhysRegClass(MCRegister Reg) const;
279 MCRegister findUnusedRegister(const MachineRegisterInfo &MRI,
292 bool isConstantPhysReg(MCRegister PhysReg) const override;
317 MCRegister getReturnAddressReg(const MachineFunction &MF) const;
345 MCRegister getVCC() const;
347 MCRegister getExec() const;
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/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.h29 class MCRegister; variable
141 MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false);
145 MCRegister getX86SubSuperRegisterOrZero(MCRegister, unsigned,
/llvm-project-15.0.7/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp71 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRRegisterClass()
82 MCRegister Reg = RISCV::F0_H + RegNo; in DecodeFPR16RegisterClass()
93 MCRegister Reg = RISCV::F0_F + RegNo; in DecodeFPR32RegisterClass()
104 MCRegister Reg = RISCV::F8_F + RegNo; in DecodeFPR32CRegisterClass()
157 MCRegister Reg = RISCV::X8 + RegNo; in DecodeGPRCRegisterClass()
168 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRPF64RegisterClass()
179 MCRegister Reg = RISCV::V0 + RegNo; in DecodeVRRegisterClass()
196 MCRegister Reg = in DecodeVRM2RegisterClass()
216 MCRegister Reg = in DecodeVRM4RegisterClass()
236 MCRegister Reg = in DecodeVRM8RegisterClass()
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h37 bool isReservedReg(const MachineFunction &MF, MCRegister Reg) const;
93 MCRegister PhysReg) const override;
94 bool isConstantPhysReg(MCRegister PhysReg) const override;
122 MCRegister Reg) const override;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h95 MCRegister PhysReg) const override;
96 bool isCallerPreservedPhysReg(MCRegister PhysReg,
145 static void emitAccCopyInfo(MachineBasicBlock &MBB, MCRegister DestReg,
146 MCRegister SrcReg);
193 bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const override { in isNonallocatableRegisterCalleeSave()

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