Home
last modified time | relevance | path

Searched refs:MCInstrDesc (Results 1 – 25 of 224) sorted by relevance

123456789

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h37 class MCInstrDesc; variable
329 const MCInstrDesc &MCID) { in BuildMI()
392 const MCInstrDesc &MCID) { in BuildMI()
402 const MCInstrDesc &MCID) { in BuildMI()
411 const MCInstrDesc &MCID) { in BuildMI()
421 const MCInstrDesc &MCID) { in BuildMI()
428 const MCInstrDesc &MCID) { in BuildMI()
445 const MCInstrDesc &MCID, bool IsIndirect,
452 const MCInstrDesc &MCID, bool IsIndirect,
459 const MCInstrDesc &MCID, bool IsIndirect,
[all …]
H A DDFAPacketizer.h44 class MCInstrDesc; variable
78 bool canReserveResources(const MCInstrDesc *MID);
82 void reserveResources(const MCInstrDesc *MID);
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.h25 class MCInstrDesc; variable
54 const MCInstrDesc &II,
69 const MCInstrDesc *II,
80 const MCInstrDesc *II,
113 const MCInstrDesc &DbgValDesc,
H A DInstrEmitter.cpp189 const MCInstrDesc &II, in CreateVirtualRegisters()
297 const MCInstrDesc *II, in AddRegisterOperand()
306 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
375 const MCInstrDesc *II, in AddOperand()
636 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); in EmitRegSequence()
719 MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc, in AddDbgValueLocationOps()
773 const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_INSTR_REF); in EmitDbgInstrRef()
887 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); in EmitDbgValueFromSingleOp()
923 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL); in EmitDbgLabel()
962 const MCInstrDesc &II = TII->get(Opc); in EmitMachineNode()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp29 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isLoadAfterStore()
39 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isLoadAfterStore()
55 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isBCTRAfterSet()
65 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isBCTRAfterSet()
85 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, in mustComeFirst()
147 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in ShouldPreferAnother()
175 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
282 const MCInstrDesc &MCID = DAG.TII->get(Opcode); in GetInstrType()
H A DPPCExpandAtomicPseudoInsts.cpp55 const MCInstrDesc &OR = TII->get(PPC::OR8); in PairedCopy()
56 const MCInstrDesc &XOR = TII->get(PPC::XOR8); in PairedCopy()
122 const MCInstrDesc &LL = TII->get(PPC::LQARX); in expandAtomicRMW128()
123 const MCInstrDesc &SC = TII->get(PPC::STQCX); in expandAtomicRMW128()
221 const MCInstrDesc &LL = TII->get(PPC::LQARX); in expandAtomicCmpSwap128()
222 const MCInstrDesc &SC = TII->get(PPC::STQCX); in expandAtomicCmpSwap128()
H A DPPCFrameLowering.cpp656 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8 in emitPrologue()
658 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD in emitPrologue()
660 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU in emitPrologue()
664 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 in emitPrologue()
673 const MCInstrDesc &HashST = in emitPrologue()
1564 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8 in emitEpilogue()
1566 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD in emitEpilogue()
1570 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 in emitEpilogue()
1572 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8 in emitEpilogue()
1576 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8 in emitEpilogue()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCInstrInfo.h33 const MCInstrDesc *Desc; // Raw array to allow static init'n
48 void InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND, in InitMCInstrInfo()
63 const MCInstrDesc &get(unsigned Opcode) const { in get()
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCInstrDesc.cpp20 bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI, in mayAffectControlFlow()
32 bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg, in hasImplicitDefOfPhysReg()
41 bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg, in hasDefOfPhysReg()
/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DMachineInstrTest.cpp55 MCInstrDesc MCID = { in TEST()
126 MCInstrDesc MCID = { in TEST()
202 MCInstrDesc MCID = {0, 1, 1, 0, 0, 0, 0, nullptr, nullptr, &OpInfo}; in TEST()
229 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr}; in TEST()
246 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr}; in TEST()
261 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr}; in TEST()
308 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr}; in TEST()
345 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr}; in TEST()
398 const MCInstrDesc MCID = { in TEST()
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp171 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); in isPredicated()
177 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); in isCPSRDefined()
187 uint64_t ARM_MC::evaluateBranchTarget(const MCInstrDesc &InstDesc, in evaluateBranchTarget()
420 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); in evaluateBranch()
444 evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode_i12()
462 const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode3()
483 const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode5()
503 evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrMode5FP16()
544 evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrModeT2_pc()
560 evaluateMemOpAddrForAddrModeT1_s(const MCInst &Inst, const MCInstrDesc &Desc, in evaluateMemOpAddrForAddrModeT1_s()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DDFAPacketizer.cpp57 bool DFAPacketizer::canReserveResources(const MCInstrDesc *MID) { in canReserveResources()
66 void DFAPacketizer::reserveResources(const MCInstrDesc *MID) { in reserveResources()
76 const MCInstrDesc &MID = MI.getDesc(); in canReserveResources()
83 const MCInstrDesc &MID = MI.getDesc(); in reserveResources()
H A DScoreboardHazardRecognizer.cpp122 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType()
177 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp160 bool shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc,
161 SmallVectorImpl<const MCInstrDesc*> &ReplInstrMCID);
218 shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc, in shouldReplaceInst()
219 SmallVectorImpl<const MCInstrDesc*> &InstDescRepl) { in shouldReplaceInst()
275 const MCInstrDesc* OriginalMCID; in shouldExitEarly()
276 SmallVector<const MCInstrDesc*, MaxNumRepl> ReplInstrMCID; in shouldExitEarly()
354 const MCInstrDesc *MulMCID, *DupMCID; in optimizeVectElement()
420 SmallVector<const MCInstrDesc*, 2> ReplInstrMCID; in optimizeVectElement()
513 SmallVector<const MCInstrDesc*, MaxNumRepl> ReplInstrMCID; in optimizeLdStInterleave()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrBuilder.h63 const MCInstrDesc &MCID = MI->getDesc();
80 const MCInstrDesc &MCID = MI->getDesc();
H A DM68kInstrInfo.h312 const MCInstrDesc &Desc, MVT MVTDst, MVT MVTSrc) const;
315 bool ExpandPUSH_POP(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
322 bool ExpandMOVEM(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h424 const MCInstrDesc &DefMCID,
428 const MCInstrDesc &DefMCID,
432 const MCInstrDesc &UseMCID,
436 const MCInstrDesc &UseMCID,
440 const MCInstrDesc &DefMCID,
442 const MCInstrDesc &UseMCID,
447 const MCInstrDesc &DefMCID, unsigned DefAdj,
450 const MCInstrDesc &UseMCID, unsigned UseAdj) const;
897 const MCInstrDesc &Desc = TII->get(Opcode); in isLegalAddressImm()
H A DMLxExpansionPass.cpp184 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
284 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
285 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
339 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions()
H A DARMHazardRecognizer.cpp31 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
52 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
55 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
/llvm-project-15.0.7/bolt/lib/Core/
H A DMCPlusBuilder.cpp333 const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode()); in getClobberedRegs()
350 const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode()); in getTouchedRegs()
370 const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode()); in getWrittenRegs()
387 const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode()); in getUsedRegs()
420 const MCInstrDesc &InstInfo = Info->get(Inst.getOpcode()); in getSrcRegs()
435 const MCInstrDesc &InstInfo = Info->get(MI.getOpcode()); in hasDefOfPhysReg()
440 const MCInstrDesc &InstInfo = Info->get(MI.getOpcode()); in hasUseOfPhysReg()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMips16InstrInfo.h24 class MCInstrDesc; variable
100 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DMCInstrDescView.h157 const MCInstrDesc &Description;
166 Instruction(const MCInstrDesc *Description, StringRef Name,
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonOptAddrMode.cpp129 const MCInstrDesc &MID = MI.getDesc(); in INITIALIZE_PASS_DEPENDENCY()
196 const MCInstrDesc &UseMID = UseMI.getDesc(); in canRemoveAddasl()
376 const MCInstrDesc &MID = MI->getDesc(); in getBaseOpPosition()
398 const MCInstrDesc &MID = MI->getDesc(); in getOffsetOpPosition()
425 const MCInstrDesc &MID = MI->getDesc(); in processAddUses()
520 const MCInstrDesc &MID = MI.getDesc(); in analyzeUses()
702 const MCInstrDesc &UseMID = UseMI->getDesc(); in changeAddAsl()
749 const MCInstrDesc &MID = UseMI->getDesc(); in xformUseMI()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp312 static bool isVCMPX64(const MCInstrDesc &Desc) { in isVCMPX64()
323 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
457 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in getSDWASrcEncoding()
568 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in getMachineOpValueCommon()
575 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in getMachineOpValueCommon()
/llvm-project-15.0.7/llvm/lib/MCA/
H A DInstrBuilder.cpp250 static void computeMaxLatency(InstrDesc &ID, const MCInstrDesc &MCDesc, in computeMaxLatency()
265 static Error verifyOperands(const MCInstrDesc &MCDesc, const MCInst &MCI) { in verifyOperands()
296 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode()); in populateWrites()
465 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode()); in populateReads()
548 const MCInstrDesc &MCDesc = MCII.get(Opcode); in createInstrDescImpl()
665 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode()); in createInstruction()

123456789