Home
last modified time | relevance | path

Searched refs:MCII (Results 1 – 25 of 111) sorted by relevance

12345

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h46 MCInstrInfo const &MCII; variable
53 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst);
180 unsigned getCVIResources(MCInstrInfo const &MCII,
187 unsigned getOtherReservedSlots(MCInstrInfo const &MCII,
224 bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI);
232 bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI);
238 bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
253 bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI);
255 bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI);
299 bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI);
[all …]
H A DHexagonMCInstrInfo.cpp41 : MCII(MCII), BundleCurrent(Inst.begin() + in PacketIterator()
47 : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()), in PacketIterator()
63 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { in operator ++()
165 HexagonMCShuffle(Context, true, MCII, STI, MCB); in canonicalizePacketImpl()
237 if (isConstExtended(MCII, MCI)) in extendIfNeeded()
238 addConstExtender(Context, MCII, MCB, MCI); in extendIfNeeded()
257 return MCII.get(MCI.getOpcode()); in getDesc()
376 return MCII.getName(MCI.getOpcode()); in getName()
638 const uint64_t V = getType(MCII, MCI); in isHVX()
931 if (!isPredicated(MCII, MCI)) in predicateInfo()
[all …]
H A DHexagonMCChecker.cpp58 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { in init()
70 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && in initReg()
77 if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) in initReg()
207 : Context(Context), MCB(mcb), RI(ri), MCII(MCII), STI(STI), in HexagonMCChecker()
215 : Context(Other.Context), MCB(Other.MCB), RI(Other.RI), MCII(Other.MCII), in HexagonMCChecker()
280 if (HexagonMCInstrInfo::isFloat(MCII, ID)) in isNeitherAnorX()
306 if (HexagonMCInstrInfo::isSoloAX(MCII, I)) { in checkAXOK()
356 if (HexagonMCInstrInfo::isCofMax1(MCII, I)) { in checkCOFMax1()
596 if (HexagonMCInstrInfo::isCVINew(MCII, I) && in checkRegisterCurDefs()
702 if (HexagonMCInstrInfo::isSolo(MCII, I)) { in checkSolo()
[all …]
H A DHexagonMCShuffler.cpp39 LLVM_DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()) in init()
41 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); in init()
44 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); in init()
63 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
66 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); in init()
106 HexagonMCShuffler MCS(Context, ReportErrors, MCII, STI, MCB); in HexagonMCShuffle()
130 bool llvm::HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII, in HexagonMCShuffle() argument
172 HexagonMCShuffler MCS(Context, false, MCII, STI, MCB); in HexagonMCShuffle()
179 bool llvm::HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII, in HexagonMCShuffle() argument
190 bool bhasDuplex = HexagonMCInstrInfo::hasDuplex(MCII, MCB); in HexagonMCShuffle()
[all …]
H A DHexagonShuffler.cpp130 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
168 MCInstrInfo const &MCII, in HexagonShuffler() argument
170 : Context(Context), BundleFlags(), MCII(MCII), STI(STI), in HexagonShuffler()
183 HexagonInstr PI(MCII, STI, &ID, Extender, S); in append()
372 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { in restrictStoreLoadOrder()
405 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()) { in restrictStoreLoadOrder()
458 if (HexagonMCInstrInfo::isRestrictSlot1AOK(MCII, ID)) in GetPacketSummary()
463 if (HexagonMCInstrInfo::prefersSlot3(MCII, ID)) { in GetPacketSummary()
475 switch (HexagonMCInstrInfo::getType(MCII, ID)) { in GetPacketSummary()
501 if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn()) in GetPacketSummary()
[all …]
H A DHexagonMCShuffler.h32 MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffler() argument
34 : HexagonShuffler(Context, ReportErrors, MCII, STI) { in HexagonMCShuffler()
39 MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffler() argument
41 : HexagonShuffler(Context, ReportErrors, MCII, STI) { in HexagonMCShuffler()
59 MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
61 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
64 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
H A DHexagonMCCodeEmitter.cpp342 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI); in parseBits()
463 unsigned InsnType = HexagonMCInstrInfo::getType(MCII, MI); in getFixupNoBits()
620 unsigned IType = HexagonMCInstrInfo::getType(MCII, MI); in getExprOpValue()
680 FixupKind = getFixupNoBits(MCII, MI, MO, VarKind); in getExprOpValue()
721 if (HexagonMCInstrInfo::isNewValue(MCII, MI) && in getMachineOpValue()
742 if (HexagonMCInstrInfo::isVector(MCII, Inst)) { in getMachineOpValue()
746 if (HexagonMCInstrInfo::hasNewValue(MCII, Inst)) in getMachineOpValue()
748 if (HexagonMCInstrInfo::hasNewValue2(MCII, Inst)) in getMachineOpValue()
754 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) { in getMachineOpValue()
758 assert(HexagonMCInstrInfo::isPredicated(MCII, MI) && in getMachineOpValue()
[all …]
H A DHexagonAsmBackend.cpp45 std::unique_ptr <MCInstrInfo> MCII; member in __anon6fd935070111::HexagonAsmBackend
67 MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *), in HexagonAsmBackend()
540 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI); in isInstRelaxable()
543 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ || in isInstRelaxable()
544 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ && in isInstRelaxable()
550 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) { in isInstRelaxable()
553 HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI)); in isInstRelaxable()
676 *MCII, CrntHMI, in relaxInstruction()
677 HexagonMCInstrInfo::getExtendableOperand(*MCII, CrntHMI)); in relaxInstruction()
746 Context, *MCII, *RF.getSubtargetInfo(), Inst, in finishLayout()
[all …]
H A DHexagonShuffler.h87 HexagonCVIResource(MCInstrInfo const &MCII,
107 HexagonInstr(MCInstrInfo const &MCII, in HexagonInstr() argument
110 : ID(id), Extender(Extender), Core(s), CVI(MCII, STI, s, id){}; in HexagonInstr()
164 MCInstrInfo const &MCII; variable
195 MCInstrInfo const &MCII, MCSubtargetInfo const &STI);
228 return (*Pred)(MCII, Inst); in HasInstWith()
/llvm-project-15.0.7/llvm/include/llvm/MCA/
H A DCustomBehaviour.h38 const MCInstrInfo &MCII; variable
41 InstrPostProcess(const MCSubtargetInfo &STI, const MCInstrInfo &MCII) in InstrPostProcess() argument
42 : STI(STI), MCII(MCII) {} in InstrPostProcess()
69 const MCInstrInfo &MCII; variable
73 const MCInstrInfo &MCII) in CustomBehaviour() argument
74 : STI(STI), SrcMgr(SrcMgr), MCII(MCII) {} in CustomBehaviour()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchMCCodeEmitter.cpp31 MCInstrInfo const &MCII; member in __anon87e3f5290111::LoongArchMCCodeEmitter
34 LoongArchMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) in LoongArchMCCodeEmitter() argument
35 : Ctx(ctx), MCII(MCII) {} in LoongArchMCCodeEmitter()
107 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
122 MCCodeEmitter *llvm::createLoongArchMCCodeEmitter(const MCInstrInfo &MCII, in createLoongArchMCCodeEmitter() argument
124 return new LoongArchMCCodeEmitter(Ctx, MCII); in createLoongArchMCCodeEmitter()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.h21 std::unique_ptr<const MCInstrInfo> const MCII; variable
25 MCInstrInfo const *MCII) in AArch64Disassembler() argument
26 : MCDisassembler(STI, Ctx), MCII(MCII) {} in AArch64Disassembler()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCCodeEmitter.cpp37 MCInstrInfo const &MCII; member in llvm::MSP430MCCodeEmitter
74 MSP430MCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) in MSP430MCCodeEmitter() argument
75 : Ctx(ctx), MCII(MCII) {} in MSP430MCCodeEmitter()
85 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
202 MCCodeEmitter *createMSP430MCCodeEmitter(const MCInstrInfo &MCII, in createMSP430MCCodeEmitter() argument
204 return new MSP430MCCodeEmitter(Ctx, MCII); in createMSP430MCCodeEmitter()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCCodeEmitter.cpp39 const MCInstrInfo &MCII; member in __anonfc7d9acb0111::WebAssemblyMCCodeEmitter
51 WebAssemblyMCCodeEmitter(const MCInstrInfo &MCII) : MCII(MCII) {} in WebAssemblyMCCodeEmitter() argument
55 MCCodeEmitter *llvm::createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII) { in createWebAssemblyMCCodeEmitter() argument
56 return new WebAssemblyMCCodeEmitter(MCII); in createWebAssemblyMCCodeEmitter()
87 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVMCCodeEmitter.cpp32 const MCInstrInfo &MCII; member in __anond047b4770111::SPIRVMCCodeEmitter
35 SPIRVMCCodeEmitter(const MCInstrInfo &mcii) : MCII(mcii) {} in SPIRVMCCodeEmitter()
53 MCCodeEmitter *llvm::createSPIRVMCCodeEmitter(const MCInstrInfo &MCII, in createSPIRVMCCodeEmitter() argument
55 return new SPIRVMCCodeEmitter(MCII); in createSPIRVMCCodeEmitter()
116 if (hasType(MI, MCII)) in encodeInstruction()
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCSchedule.cpp68 const MCInstrInfo &MCII, in computeInstrLatency() argument
70 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in computeInstrLatency()
77 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in computeInstrLatency()
111 const MCInstrInfo &MCII, in getReciprocalThroughput() argument
113 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in getReciprocalThroughput()
123 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in getReciprocalThroughput()
/llvm-project-15.0.7/llvm/unittests/tools/llvm-mca/
H A DMCATestBase.cpp51 MCII.reset(TheTarget->createMCInstrInfo()); in SetUp()
52 ASSERT_TRUE(MCII); in SetUp()
54 MCIA.reset(TheTarget->createMCInstrAnalysis(MCII.get())); in SetUp()
58 *MAI, *MCII, *MRI)); in SetUp()
67 mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get()); in runBaselineMCA()
95 auto CB = std::make_unique<mca::CustomBehaviour>(*STI, SM, *MCII); in runBaselineMCA()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp33 const MCInstrInfo &MCII; member in __anon58b697d50111::R600MCCodeEmitter
37 : MRI(mri), MCII(mcii) {} in R600MCCodeEmitter()
82 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, in createR600MCCodeEmitter() argument
84 return new R600MCCodeEmitter(MCII, *Ctx.getRegisterInfo()); in createR600MCCodeEmitter()
90 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
161 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp62 const MCInstrInfo &MCII) in AMDGPUCustomBehaviour() argument
63 : CustomBehaviour(STI, SrcMgr, MCII) { in AMDGPUCustomBehaviour()
197 << MCII.getName(Opcode) << " will be completely " in computeWaitCnt()
246 const MCInstrDesc &MCID = MCII.get(Opcode); in generateWaitCntInfo()
338 const MCInstrInfo &MCII) { in createAMDGPUCustomBehaviour() argument
339 return new AMDGPUCustomBehaviour(STI, SrcMgr, MCII); in createAMDGPUCustomBehaviour()
344 const MCInstrInfo &MCII) { in createAMDGPUInstrPostProcess() argument
345 return new AMDGPUInstrPostProcess(STI, MCII); in createAMDGPUInstrPostProcess()
H A DAMDGPUCustomBehaviour.h31 AMDGPUInstrPostProcess(const MCSubtargetInfo &STI, const MCInstrInfo &MCII) in AMDGPUInstrPostProcess() argument
32 : InstrPostProcess(STI, MCII) {} in AMDGPUInstrPostProcess()
87 const mca::SourceMgr &SrcMgr, const MCInstrInfo &MCII);
/llvm-project-15.0.7/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.h39 AVRMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx) in AVRMCCodeEmitter() argument
40 : MCII(MCII), Ctx(Ctx) {} in AVRMCCodeEmitter()
108 const MCInstrInfo &MCII; variable
H A DAVRMCELFStreamer.h26 std::unique_ptr<MCInstrInfo> MCII; variable
34 MCII(createAVRMCInstrInfo()) {} in AVRMCELFStreamer()
42 MCII(createAVRMCInstrInfo()) {} in AVRMCELFStreamer()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp45 std::unique_ptr<MCInstrInfo const> const MCII; member in __anon0dab59a40111::HexagonDisassembler
50 MCInstrInfo const *MCII) in HexagonDisassembler() argument
51 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *), in HexagonDisassembler()
65 MCInstrInfo MCII = *Disassembler.MCII; in fullValue() local
67 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) in fullValue()
200 HexagonMCChecker Checker(getContext(), *MCII, STI_, MI, in getInstruction()
469 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { in getSingleInstruction()
480 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); in getSingleInstruction()
500 if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { in getSingleInstruction()
530 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && in getSingleInstruction()
[all …]
/llvm-project-15.0.7/llvm/tools/llvm-mca/
H A Dllvm-mca.cpp402 std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo()); in main() local
403 assert(MCII && "Unable to create instruction info!"); in main()
406 TheTarget->createMCInstrAnalysis(MCII.get())); in main()
462 Triple(TripleName), AssemblerDialect, *MAI, *MCII, *MRI)); in main()
485 TheTarget->createInstrPostProcess(*STI, *MCII)); in main()
490 IPP = std::make_unique<mca::InstrPostProcess>(*STI, *MCII); in main()
494 mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get()); in main()
507 TheTarget->createMCCodeEmitter(*MCII, Ctx)); in main()
601 TheTarget->createCustomBehaviour(*STI, S, *MCII)); in main()
605 CB = std::make_unique<mca::CustomBehaviour>(*STI, S, *MCII); in main()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86AsmBackend.cpp122 std::unique_ptr<const MCInstrInfo> MCII; member in __anona43f623f0111::X86AsmBackend
141 MCII(T.createMCInstrInfo()) { in X86AsmBackend()
243 const MCInstrDesc &Desc = MCII.get(Opcode); in getCondFromBranch()
252 X86::CondCode CC = getCondFromBranch(MI, MCII); in classifySecondInstInMacroFusion()
259 const MCInstrDesc &Desc = MCII.get(Opcode); in isRIPRelative()
279 if (isRIPRelative(Inst, MCII)) in isFirstMacroFusibleInst()
298 const MCInstrDesc &Desc = MCII->get(Inst.getOpcode()); in determinePaddingPrefix()
354 if (!isFirstMacroFusibleInst(Cmp, *MCII)) in isMacroFused()
359 classifySecondInstInMacroFusion(Jcc, *MCII); in isMacroFused()
464 if (isPrefix(PrevInst, *MCII)) in canPadInst()
[all …]

12345