Lines Matching refs:MCII

342   bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);  in parseBits()
406 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() && in EncodeSingleInstruction()
409 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); in EncodeSingleInstruction()
418 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); in EncodeSingleInstruction()
460 MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO, in getFixupNoBits() argument
462 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); in getFixupNoBits()
463 unsigned InsnType = HexagonMCInstrInfo::getType(MCII, MI); in getFixupNoBits()
474 const MCInstrDesc &NextD = HexagonMCInstrInfo::getDesc(MCII, NextI); in getFixupNoBits()
476 HexagonMCInstrInfo::getType(MCII, NextI) == HexagonII::TypeCR) in getFixupNoBits()
582 bool InstExtendable = HexagonMCInstrInfo::isExtendable(MCII, MI) || in getExprOpValue()
583 HexagonMCInstrInfo::isExtended(MCII, MI); in getExprOpValue()
597 if (OpIdx == HexagonMCInstrInfo::getExtendableOp(MCII, MI)) { in getExprOpValue()
598 unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); in getExprOpValue()
615 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); in getExprOpValue()
616 unsigned FixupWidth = HexagonMCInstrInfo::getExtentBits(MCII, MI) - in getExprOpValue()
617 HexagonMCInstrInfo::getExtentAlignment(MCII, MI); in getExprOpValue()
620 unsigned IType = HexagonMCInstrInfo::getType(MCII, MI); in getExprOpValue()
623 << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI) in getExprOpValue()
639 unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); in getExprOpValue()
672 FixupKind = HexagonMCInstrInfo::isExtentSigned(MCII, MI) in getExprOpValue()
680 FixupKind = getFixupNoBits(MCII, MI, MO, VarKind); in getExprOpValue()
721 if (HexagonMCInstrInfo::isNewValue(MCII, MI) && in getMachineOpValue()
722 &MO == &HexagonMCInstrInfo::getNewValueOperand(MCII, MI)) { in getMachineOpValue()
742 if (HexagonMCInstrInfo::isVector(MCII, Inst)) { in getMachineOpValue()
746 if (HexagonMCInstrInfo::hasNewValue(MCII, Inst)) in getMachineOpValue()
747 DefReg1 = HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg(); in getMachineOpValue()
748 if (HexagonMCInstrInfo::hasNewValue2(MCII, Inst)) in getMachineOpValue()
749 DefReg2 = HexagonMCInstrInfo::getNewValueOperand2(MCII, Inst).getReg(); in getMachineOpValue()
754 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) { in getMachineOpValue()
758 assert(HexagonMCInstrInfo::isPredicated(MCII, MI) && in getMachineOpValue()
760 if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) == in getMachineOpValue()
761 HexagonMCInstrInfo::isPredicatedTrue(MCII, MI)) in getMachineOpValue()
766 unsigned Offset = HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset in getMachineOpValue()
776 switch (HexagonMCInstrInfo::getDesc(MCII, MI).OpInfo[OperandNumber].RegClass) { in getMachineOpValue()