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Searched refs:LoopHasReductions (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonTargetTransformInfo.h97 bool enableAggressiveInterleaving(bool LoopHasReductions) { in enableAggressiveInterleaving() argument
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.h88 bool enableAggressiveInterleaving(bool LoopHasReductions);
H A DPPCTargetTransformInfo.cpp825 bool PPCTTIImpl::enableAggressiveInterleaving(bool LoopHasReductions) { in enableAggressiveInterleaving() argument
830 return LoopHasReductions; in enableAggressiveInterleaving()
/llvm-project-15.0.7/llvm/include/llvm/Analysis/
H A DTargetTransformInfo.h790 bool enableAggressiveInterleaving(bool LoopHasReductions) const;
1641 virtual bool enableAggressiveInterleaving(bool LoopHasReductions) = 0;
2106 bool enableAggressiveInterleaving(bool LoopHasReductions) override { in enableAggressiveInterleaving() argument
2107 return Impl.enableAggressiveInterleaving(LoopHasReductions); in enableAggressiveInterleaving()
H A DTargetTransformInfoImpl.h345 bool enableAggressiveInterleaving(bool LoopHasReductions) const { in enableAggressiveInterleaving() argument
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp532 bool LoopHasReductions) const { in enableAggressiveInterleaving()
533 return TTIImpl->enableAggressiveInterleaving(LoopHasReductions); in enableAggressiveInterleaving()