Home
last modified time | relevance | path

Searched refs:Latency (Results 1 – 25 of 866) sorted by relevance

12345678910>>...35

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleA57WriteRes.td14 // Latency: #cyc
63 let Latency = Lat;
70 let Latency = Lat;
96 let Latency = 6;
101 let Latency = 6;
106 let Latency = 7;
111 let Latency = 8;
116 let Latency = 9;
120 let Latency = 9;
124 let Latency = 8;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedA57WriteRes.td14 // Latency: #cyc
70 let Latency = 6;
75 let Latency = 7;
80 let Latency = 8;
84 let Latency = 9;
88 let Latency = 8;
92 let Latency = 6;
96 let Latency = 6;
100 let Latency = 6;
104 let Latency = 6;
[all …]
H A DAArch64SchedKryoDetails.td16 let Latency = 3; let NumMicroOps = 2;
23 let Latency = 3; let NumMicroOps = 2;
30 let Latency = 4; let NumMicroOps = 3;
66 let Latency = 3; let NumMicroOps = 2;
72 let Latency = 3; let NumMicroOps = 2;
78 let Latency = 2; let NumMicroOps = 2;
84 let Latency = 2; let NumMicroOps = 2;
90 let Latency = 2; let NumMicroOps = 2;
96 let Latency = 3; let NumMicroOps = 4;
102 let Latency = 5; let NumMicroOps = 4;
[all …]
H A DAArch64SchedKryo.td69 { let Latency = 2; let NumMicroOps = 2; }
71 { let Latency = 2; let NumMicroOps = 2; }
73 { let Latency = 2; let NumMicroOps = 2; }
79 def : WriteRes<WriteIM32, [KryoUnitX]> { let Latency = 5; }
80 def : WriteRes<WriteIM64, [KryoUnitX]> { let Latency = 5; }
90 { let Latency = 3; let NumMicroOps = 2; }
96 { let Latency = 6; let NumMicroOps = 2; }
104 def : WriteRes<WriteSys, []> { let Latency = 1; }
105 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
106 def : WriteRes<WriteHint, []> { let Latency = 1; }
[all …]
H A DAArch64SchedAmpere1.td58 let Latency = 1;
63 let Latency = 1;
68 let Latency = 1;
73 let Latency = 1;
78 let Latency = 1;
83 let Latency = 1;
88 let Latency = 1;
93 let Latency = 2;
98 let Latency = 2;
103 let Latency = 2;
[all …]
H A DAArch64SchedExynosM3.td111 def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0;
113 def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
209 M3UnitD]> { let Latency = 12;
212 M3UnitD]> { let Latency = 21;
214 def : WriteRes<WriteIM32, [M3UnitC]> { let Latency = 3; }
215 def : WriteRes<WriteIM64, [M3UnitC]> { let Latency = 4;
227 def : WriteRes<WriteLDHi, []> { let Latency = 4;
254 M3UnitFST]> { let Latency = 1;
263 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
264 def : WriteRes<WriteHint, []> { let Latency = 1; }
[all …]
H A DAArch64SchedExynosM4.td136 def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
137 def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
139 def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
178 def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4;
191 M4UnitL]> { let Latency = 5;
194 M4UnitL]> { let Latency = 5;
198 M4UnitL]> { let Latency = 5;
201 M4UnitL]> { let Latency = 4;
567 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
568 def : WriteRes<WriteHint, []> { let Latency = 1; }
[all …]
H A DAArch64SchedTSV110.td198 let Latency = 1;
204 let Latency = 2;
210 let Latency = 2;
216 let Latency = 2;
222 let Latency = 2;
228 let Latency = 4;
234 let Latency = 4;
240 let Latency = 4;
252 let Latency = 6;
258 let Latency = 6;
[all …]
H A DAArch64SchedExynosM5.td136 def M5WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
137 def M5WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
139 def M5WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
196 def M5WriteCA : SchedWriteRes<[M5UnitC]> { let Latency = 3;
210 M5UnitL]> { let Latency = 6;
213 M5UnitL]> { let Latency = 6;
217 M5UnitL]> { let Latency = 6;
220 M5UnitL]> { let Latency = 4;
602 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
603 def : WriteRes<WriteHint, []> { let Latency = 1; }
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dmisched-fp-basic.ll19 ; CHECK_A9: Latency : 5
20 ; CHECK_SWIFT: Latency : 4
21 ; CHECK_R52: Latency : 6
26 ; CHECK_SWIFT: Latency : 4
27 ; CHECK_A9: Latency : 6
28 ; CHECK_R52: Latency : 6
33 ; CHECK_R52: Latency : 7
36 ; CHECK_SWIFT: Latency : 4
37 ; CHECK_A9: Latency : 5
38 ; CHECK_R52: Latency : 6
[all …]
H A Dmisched-int-basic-thumb2.mir41 # CHECK_A9: Latency : 2
42 # CHECK_SWIFT: Latency : 2
43 # CHECK_R52: Latency : 2
46 # CHECK_A9: Latency : 1
47 # CHECK_SWIFT: Latency : 3
48 # CHECK_R52: Latency : 4
51 # CHECK_A9: Latency : 1
52 # CHECK_SWIFT: Latency : 1
53 # CHECK_R52: Latency : 3
56 # CHECK_A9: Latency : 0
[all …]
H A Dcortex-a57-misched-vfma.ll16 ; CHECK-SAME: Latency=0
25 ; CHECK-SAME: Latency=4
33 ; CHECK-SAME: Latency=9
55 ; CHECK-SAME: Latency=0
64 ; CHECK-SAME: Latency=4
72 ; CHECK-SAME: Latency=9
93 ; CHECK-SAME: Latency=0
102 ; CHECK-SAME: Latency=4
110 ; CHECK-SAME: Latency=9
132 ; CHECK-SAME: Latency=0
[all …]
H A Dmisched-int-basic.mir32 # CHECK_A9: Latency : 2
33 # CHECK_SWIFT: Latency : 4
34 # CHECK_R52: Latency : 4
37 # CHECK_A9: Latency : 2
38 # CHECK_SWIFT: Latency : 4
39 # CHECK_R52: Latency : 4
42 # CHECK_A9: Latency : 1
43 # CHECK_SWIFT: Latency : 1
44 # CHECK_R52: Latency : 3
47 # CHECK_A9: Latency : 2
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCScheduleE5500.td52 [5, 2, 2], // Latency = 1
57 [5, 2, 2], // Latency = 1
62 [5, 2, 2, 2], // Latency = 1
68 [6, 2, 2], // Latency = 1 or 2
117 [5, 2, 2], // Latency = 1
141 [5, 2], // Latency = 1
145 [5, 2, 2], // Latency = 1
150 [5, 2], // Latency = 1
154 [5, 2, 2], // Latency = 1
170 [7, 2], // Latency = 3
[all …]
H A DPPCScheduleE500mc.td48 [4, 1, 1], // Latency = 1
53 [4, 1, 1], // Latency = 1
75 [11], // Latency = 8
112 [4, 1], // Latency = 1
121 [4, 1], // Latency = 1
133 [6, 1], // Latency = 3
137 [6, 1], // Latency = 3
141 [6, 1], // Latency = 3
146 [6, 1], // Latency = 3
152 [6, 1], // Latency = 3
[all …]
H A DPPCScheduleE500.td43 [4, 1, 1], // Latency = 1
48 [4, 1, 1], // Latency = 1
99 [4, 1], // Latency = 1
108 [4, 1], // Latency = 1
120 [6, 1], // Latency = 3
124 [6, 1], // Latency = 3
128 [6, 1], // Latency = 3
133 [6, 1], // Latency = 3
139 [6, 1], // Latency = 3
144 [6, 1], // Latency = 3
[all …]
H A DPPCScheduleP9.td138 let Latency = 1;
145 let Latency = 1;
152 let Latency = 1;
158 let Latency = 1;
163 let Latency = 1;
169 let Latency = 1;
174 let Latency = 1;
179 let Latency = 1;
184 let Latency = 1;
194 let Latency = 2;
[all …]
H A DPPCScheduleP10.td92 let Latency = 7;
97 let Latency = 22;
102 let Latency = 24;
107 let Latency = 26;
112 let Latency = 27;
117 let Latency = 36;
122 let Latency = 2;
127 let Latency = 7;
133 let Latency = 13;
270 let Latency = 5;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86SchedSkylakeClient.td169 let Latency = 2;
426 let Latency = 2;
431 let Latency = 6;
437 let Latency = 3;
441 let Latency = 2;
545 let Latency = 4;
556 let Latency = 8;
579 let Latency = 6;
625 let Latency = 1;
640 let Latency = 1;
[all …]
H A DX86SchedHaswell.td156 let Latency = !add(HWWriteIMulH.Latency, HaswellModel.LoadLatency);
188 let Latency = 2;
486 let Latency = 2;
491 let Latency = 6;
497 let Latency = 2;
501 let Latency = 2;
563 let Latency = 7;
681 let Latency = 7;
740 let Latency = 4;
748 let Latency = 4;
[all …]
H A DX86SchedBroadwell.td186 let Latency = 2;
487 let Latency = 2;
492 let Latency = 6;
497 let Latency = 2;
501 let Latency = 2;
563 let Latency = 7;
626 let Latency = 1;
634 let Latency = 1;
642 let Latency = 1;
649 let Latency = 1;
[all …]
H A DX86SchedSkylakeServer.td170 let Latency = 2;
427 let Latency = 2;
432 let Latency = 6;
438 let Latency = 3;
442 let Latency = 2;
546 let Latency = 4;
557 let Latency = 8;
580 let Latency = 6;
626 let Latency = 1;
654 let Latency = 1;
[all …]
H A DX86SchedIceLake.td178 let Latency = 2;
435 let Latency = 2;
440 let Latency = 6;
446 let Latency = 3;
450 let Latency = 2;
554 let Latency = 4;
565 let Latency = 8;
588 let Latency = 6;
634 let Latency = 1;
662 let Latency = 1;
[all …]
H A DX86SchedSandyBridge.td181 let Latency = 2;
453 let Latency = 2;
457 let Latency = 7;
462 let Latency = 3;
466 let Latency = 5;
522 let Latency = 4;
538 let Latency = 7;
560 let Latency = 8;
603 let Latency = 1;
613 let Latency = 1;
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dmisched-fusion-arith-logic.mir16 ; CHECK: SU(2): Ord Latency=0 Cluster
19 ; CHECK: SU(3): Ord Latency=0 Cluster
22 ; CHECK: SU(0): Ord Latency=0 Cluster
25 ; CHECK: SU(1): Ord Latency=0 Cluster
38 ; CHECK: SU(2): Ord Latency=0 Cluster
41 ; CHECK: SU(3): Ord Latency=0 Cluster
44 ; CHECK: SU(0): Ord Latency=0 Cluster
47 ; CHECK: SU(1): Ord Latency=0 Cluster
60 ; CHECK: SU(2): Ord Latency=0 Cluster
63 ; CHECK: SU(3): Ord Latency=0 Cluster
[all …]

12345678910>>...35