Searched refs:LastStage (Results 1 – 6 of 6) sorted by relevance
| /llvm-project-15.0.7/llvm/include/llvm/MC/ |
| H A D | MCInstrItineraries.h | 101 uint16_t LastStage; ///< Index of last + 1 stage in itinerary member
131 (Itineraries[ItinClassIndx].LastStage == UINT16_MAX)); in isEndMarker()
142 unsigned StageIdx = Itineraries[ItinClassIndx].LastStage; in endStage()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ModuloSchedule.h | 191 void generateProlog(unsigned LastStage, MachineBasicBlock *KernelBB,
193 void generateEpilog(unsigned LastStage, MachineBasicBlock *KernelBB,
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | ModuloSchedule.cpp | 185 void ModuloScheduleExpander::generateProlog(unsigned LastStage, in generateProlog() argument
195 for (unsigned i = 0; i < LastStage; ++i) { in generateProlog()
244 unsigned LastStage, MachineBasicBlock *KernelBB, MachineBasicBlock *OrigBB, in generateEpilog() argument
268 int EpilogStage = LastStage + 1; in generateEpilog()
269 for (unsigned i = LastStage; i >= 1; --i, ++EpilogStage) { in generateEpilog()
282 for (unsigned StageNum = i; StageNum <= LastStage; ++StageNum) { in generateEpilog()
298 InstrMap, LastStage, EpilogStage, i == 1); in generateEpilog()
300 LastStage, EpilogStage, i == 1); in generateEpilog()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | GCNSchedStrategy.h | 83 LastStage = PreRARematerialize enumerator
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 436 int Size = II[SchedClass].LastStage - II[SchedClass].FirstStage; in getCVIResources()
442 unsigned Stage = II[SchedClass].LastStage - 1; in getCVIResources()
472 Stage < II[SchedClass].LastStage; ++Stage) { in getOtherReservedSlots()
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | SubtargetEmitter.cpp | 630 Intinerary.LastStage << ", " << in EmitItineraries()
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